CS150 — Final Exam Review

Albert Magyar

December 13, 2012

Digital logic

F = Sm(3,4,5,6,8,10,12,14,15)

F = Σm(3, 4, 5, 6, 11, 12, 13, 14)

Starting a K-map – truth values filled in

0 0 1 0

1 1 0 1

1 1 0 1

0 0 1 0

00

00

01

01

11

11

10

10

AB

CD

Grouped K-map with red, green, and blue shading

0 0 1 0

1 1 0 1

1 1 0 1

0 0 1 0

00

00

01

01

11

11

10

10

AB

CD

F = BC + BD + BCD

NAND implementation

Decompose into ternary NAND of three intermediate functions.

F = BC + BD + BCD

F = X + Y + Z

F = (X Y Z )

F = NAND3(X , Y , Z )

NAND implementation

X = BC =⇒ X = NAND2(B, C )

Y = BD =⇒ Y = NAND2(B, D)

Z = BCD =⇒ Z = NAND3(BCD)

NAND implementation

Putting it all together:

CMOS implementation

Use SOP to draw pull-up (taking care to invert each signal)

F = BC + BD + BCD

CMOS implementation – could be better still (but okay)

Swap parallel for serial to draw pull-down with NMOS.

F = BC + BD + BCD

FSM

Part a): The purpose of this FSM is to detect the pattern 0110.It does not detect overlapping patterns.

Part b)

assign out = (current state == STATE 3) && in;

always @(posedge clk) begin

if (rst) current state <= STATE 0;

else current state <= next state;

end

always @(*) begin

case (current state)

STATE 0 : next state = in ? STATE 0 : STATE 1;

STATE 1 : next state = in ? STATE 2 : STATE 1;

STATE 2 : next state = in ? STATE 3 : STATE 1;

default : next state = STATE 0;

endcase

end

Logic-level implementation

Create per-bit truth tables for next state:

cs1 cs0 in ns00 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 0

ns0 = cs1 · ¯cs0 + ¯cs1 · in

Logic-level implementation

cs1 cs0 in ns10 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 0

ns1 = cs1 · ¯cs0 · in + ¯cs1 · cs0 · in

Logic-level implementation

Moore machine: add output high state

Ready/valid

a.) 4′b0000, 4′b0110, 4′b0110

b.) 0, 4, 5

Downsampler control

Downsampler control

Very simple datapath:

I An odd number of inputs would mean that the controllerwould either hang or would combine the first input of the next‘line’ with the last input of the first ‘line.’

I This could be solved by making DataInValid andDataOutValid multi-bit so that there could be an‘end-of-line’ value for valid.

Downsampler control

Very simple datapath:

I An odd number of inputs would mean that the controllerwould either hang or would combine the first input of the next‘line’ with the last input of the first ‘line.’

I This could be solved by making DataInValid andDataOutValid multi-bit so that there could be an‘end-of-line’ value for valid.

Memory operations

a.) lui $t0, 0x3000

addiu $t0, $t0, 0x20

lw $t0, 40($t0)

Read – all three masks 4’b0000.

b.) lui $t0, 0x1000

addiu $t0, $t0, 0x20

sb $t0, 43($t0)

Store byte to 0x10000063IMEM 4’b0000, DMEM 4’b0001, ISRMEM 4’b0000

c.) lui $t0, 0x3000

sh $t0, 42($t0)

Store half to 0x30000042IMEM 4’b0011, DMEM 4’b0011, ISRMEM 4’b0000

Memory timings

Given the 5-3-3-8 200MHz SDRAM as implemented in yourproject, and assuming what is the fastest clock speed that yourMIPS processor could run and never stall waiting for a fetch fromSDRAM? Assume that you can completely redesign the controllogic optimally.

I tCL = tCAS = 5 The time between writing a column addressand the first bit of data coming out – this is the period ofsequential bursts.

I tRCD = 3 Time between writing row address and writingcolumn address.

I tRP = 3 Time between writing precharge command (‘closing’old row) and writing row address (‘opening’ new row).

I tRAS = 8 Time between writing row address (‘opening’ row)and writing precharge (‘closing’ row).

Memory timings

I Assuming every fetch is completely random in the addressspace, might have to write precharge, wait tRP to write row,wait tRCD to write column, and wait tCL to get data.

I Also, the time tRCD + tCL we have the row open must belonger than tRAS to close the row.

I This has total latency t = 3 + 3 + 5 = 11 in units of 200 MHzclock periods.

I Assuming every fetch is completely random, this latency is alower bound on the minimum CPU clock period.

11 ∗ 5 ns = 55 ns =⇒ fmax = 18.2 MHz

Memory timings

Given a 5-5-5-12 SDRAM, how fast would its clock need to run tomatch the read cycle time of the SDRAM in problem 1?

tRP + tRCD + tCLf

=t ′RP + t ′RCD + t ′CL

f ′

3 + 3 + 5

200 MHz=

5 + 5 + 5

f ′

f ′ =15

11× 200 MHz

f ′ = 273 MHz

Memory timings

How long does it take to refresh a single row in the SDRAM inproblem 1?

I Time to refresh is simply tRASI This is why the row must be active for tRAS or longer!