Company Confidential

FL7733 EVT1 System Verification ReportOct.29.2013

Power Conversion Korea

Inki-Park

2 Company Confidential

Schematics[8.4W]

F11A/250V

NP NS

NA

C2

/10uF

R4

/200kΩ

R5

/30kΩ

R6

/10Ω

Rcs21.5Ω

D2

/1N4003

C4 /5pF

CF2/47nF

C1

/68nF

L

N

LF1/10mH

Q1/FQU5N60C

1

COMI

HV

NC

VDD

CSGND

Gate

VS7

8

5

6 2

3

4

U1/FL7733 EVT0

RS1

/100kΩ

DS1

/RS1M

CS1

/20nF Co1/470uF

Do1/ES3D

C3

/10nF

MOV1/470

BD1/MB6S

C5 /2.2uF

Cy12.2nF

CF1/47nF Ro1

/20kΩ

R2 /30kΩ

R1 /30kΩ

Rcs12.0Ω

RS2

/100kΩ

Co2/NC

T1

+

Rcomp

/220Ω

3 Company Confidential

Transformer Core : RM6 Inductance of Primary side : 1mH

Top View

5 4

3

21

6

RM6 (PC47)

2

NP21

65

NS

3

NS+

NA

NS-

NP1

NP1(6 à 1)

NS + à NS -

NA(5à 3)

NP1(1à 2)

No Winding Pin(S → F) Wire Turns Winding Method

1 NP1 6 1 0.20φ 54Ts Solenoid winding

2 Insulation : Polyester Tape t = 0.025mm, 2Layers

3 NS NS + NS- 0.25φ (TIW) 30Ts Solenoid winding

4 Insulation : Polyester Tape t = 0.025mm, 2Layers

5 NA 5 3 0.16φ 20Ts Solenoid winding

6 Insulation : Polyester Tape t = 0.025mm, 2Layers

7 NP2 1 2 0.20φ 27Ts Solenoid winding

8 Insulation : Polyester Tape t = 0.025mm, 6Layers

Transformer[8.4W]

4 Company Confidential

1. Protection1) SCP2) SRSP3) SROP4) ODSP5) VS OVP

5 Company Confidential

SCP Concept

VS voltage at gate-off is close to zero when LED load is shorted. SCP is disabled for the initial 14 ms once VDD is higher than UVLO. 200ms JFET regulation enlarges AR time during SCP.

14msTimer

0.3V

S/HSCP

+

-VS

VDD200msSS Timer

16V/7.75V

VDD

10/19V8 HV

4

5

+

-

SCP is disabled for initial 14 ms

LED short

14ms

VDD OFF

VDD ON

Gate

200ms JFET regulation

19V

10V

VDD

VCS

0.2V

VIN

14ms

6 Company Confidential

SCP Test Results

SCP de-bounce cycle is 4 and operated well.

Test condition: CCOMI[2.2uF], CVDD[10uF].

Vin[90Vac]

Ch1[VGATE],,Ch2[VIN], Ch3[VVS], Ch4[IOUT]

Vin[265Vac]

7 Company Confidential

SCP Test Results

TSCP.bnk of EVT1 was larger than EVT0. JFET regulation is operated well.

Test condition: , Rstr[30k], CCOMI[1.0uF], CVDD[10uF].

TSCP.bnk:14ms -->OK

Ch1[VDD],,Ch2[VIN], Ch3[VGATE], Ch4[IOUT]

EVT0

Ch1[VGATE],,Ch2[VIN], Ch3[VDD], Ch4[IOUT]

EVT1

TSCP.bnk:16ms

VJFET.HL : 19V

VJFET.LL : 13V

8 Company Confidential

Current-mode SRSP

Current-mode SRSP protects the condition that sensing resistor is short before VDD-ON. Vin level is be detected by Ivs and TVCS-BNK is inversely proportional to Vin level. Once VCS is maintained under 0.1V for TVCS-BNK, SRSP is triggered. Current-mode SRSP is monitored only for first switching cycle.

Vcs

0.1V

TVCS-BNK

SRSP

High Ivs

Low Ivs

Vcs

0.1V

SRSP

Gate

TVCS-BNK

RS Short

Normal RS

RS Short

Normal RS

Gate

NA

Rvs2

Vcs Blanking Time

DETINBNKVCS V

T.

1

Vcs

0.1V

Shut Down

Rvs1Ivs

Current Mirror

VIN.DET

First GATE signal

VS5

RS

CS5

Concept

9 Company Confidential

Test Results

SRSP is operated well. JFET regulation is operated well.

Test condition: CCOMI[2.2uF], CVDD[10uF].

TonSRSP: 4.2us VJFET.HL : 19V

Current-mode SRSP

Vin[90Vac]

Vin[265Vac]

Vin[265Vac]

Ch1[VDD],,Ch2[VIN], Ch3[VCS], Ch4[IOUT]

TonSRSP: 1.9us

VJFET.LL : 13V

10 Company Confidential

Voltage-mode SRSP

Voltage-mode SRSP protects the condition that sensing resistor is short after VDD-ON. SRSP monitoring is enabled when Vin is higher than 60% of peak Vin. Once VCS is maintained under 0.1V for SRSP monitoring time, SRSP is triggered.

NA

Rvs2

VIN.DET peak detection

Vcs

0.1V

Shut Down

Rvs1Ivs

Current Mirror

VIN.DET

VS5

RS

CS5

VIN.DET.PK

4R

6R

Gate

VCS

0.1V

VIN.DET.PKVIN.DET

60% VIN.DET.PK

Sensing resistor

short

SRSP enabled area

Concept

11 Company Confidential

Test Results

Voltage mode SRSP is operated well

Test condition: CCOMI[2.2uF], CVDD[10uF].

Vcs < 0.1V

Rcs Short

Ch1[VDD],,Ch2[VGATE], Ch3[VCS], Ch4[IOUT]

a b

a

b

Rcs Short

SRSP Trigger

Vin: a<b Vcs: a>b

A B

A

B

Vin: a<b Vcs: a>b

Vin: 83V[≈130V *0.6] Vin: 248V[≈368V *0.6]

Vcs < 0.1V

SRSP Trigger

Vin[265Vac]Vin[90Vac]

Voltage-mode SRSP

12 Company Confidential

Test Results

SROP is operated well. JFET regulation is operated well.

Test condition: CCOMI[2.2uF], CVDD[10uF].

Ch1[VGATE],,Ch2[VDD], Ch3[VCS], Ch4[IOUT]

SROP

1.0us/div 100ms/div

13 Company Confidential

Test Results

OCP is triggered with just one pulse. JFET regulation is operated well.

OCP[ODSP]

Ch1[VGATE],,Ch2[VCS], Ch3[VIN], Ch4[IOUT]

Test condition: Vin[265Vac], CCOMI[2.2uF], CVDD[10uF]. Csn[20nF], Rsn[100k]

1.0us/div 100ms/div

VJFET.HL : 19V

VJFET.LL : 13V

14 Company Confidential

Test Results

After LED opened, VDD OVP is triggered at 24.8V. VS OVP is also triggered at 3.1V after LED opened.

Test condition: CCOMI[2.2uF], CVDD[10uF].

OVP – VDD and VS

VDD OVP VS OVP

VDD: 24.8V

LED Open

Ch1[VGATE],,Ch2[VDD], Ch3[VVS], Ch4[IOUT]

VVS: 1.56V

VDD: 17.3VLED Open

VVS: 3.1V

15 Company Confidential

Test Results

JFET regulation is operated well.

Test condition: CCOMI[2.2uF], CVDD[10uF].

OVP – VDD and VS

Ch1[VGATE],,Ch2[VDD], Ch3[VVS], Ch4[IOUT]

VJFET.HL : 19V

VJFET.LL : 13V

16 Company Confidential

2. System1) CC2) THD/PF3) Overshoot 4) Startup

17 Company Confidential

±1.05%

CC1. Test results

Test condition: RVS1[200k], RVS2[30k], COUT[470uF], CCOMI[2.2uF]

265Vac[50Hz] 230Vac[50Hz]

180Vac[50Hz]

140Vac[60Hz]

120Vac[60Hz] 90Vac[60Hz]

Rcomp[200Ω] ±1.02% ±0.88% ±1.18% ±1.19% ±1.04% ±1.19%

Rcomp[220Ω] ±1.78% ±1.48% ±1.33% ±1.34% ±1.19% ±1.49%

±0.59%

Rcomp[200Ω] Rcomp[220Ω]

18 Company Confidential

CC1. Test results

Test condition: RVS1[200k], RVS2[30k], COUT[470uF], CCOMI[2.2uF]

±0.59%

EVT0 EVT1

Load regulation of EVT1 is having different pattern a little from EVT0.

±0.6%

19 Company Confidential

THD and PF

SamplesIo [mA] PF THD[%]

90Vac 265Vac 90Vac 265Vac 90Vac 265Vac

#01 336 339 0.997 0.904 3.65 7.73

#02 334 335 0.997 0.901 3.53 7.96

1. Test results Test condition: CCOMI[2.2uF]

Vin[90Vac] Vin[265Vac]

Ch3[VIN], Ch4[IIN]

20 Company Confidential

Overshoot

VCOMI

VIN

VDD = VDD_ON

90Vac

265Vac

13ms

pkIvsV MCOMI .

1.

18 ms Startup Time

1.1 V

Vin level is detected by Ivs and VCOMI is charged by VCOMI modulator output. VCOMI modulator output is inversely proportional to Vin level. Therefore, VCOMI is adjusted close to steady state level during softstart time.

NA

Rvs2

VCOMI

Modulator

pkIvsV MCOMI .

1.

Rvs1

Ivs

VS5

IVS peak Detector

13ms counter

1.1V

COMI6

+

-

VDD

16V/7.75V

4

18ms SS counter

Concept

21 Company Confidential

Test Results

VCOMI clamped at startup is inverse proportional to Vin level and operated well. There are no overshoot even fast On & OFF of AC power.

Vin[90Vac]

Vin[265Vac]

Vin[277Vac]

Overshoot – 8.4W

VCOMI_INT.CLP: 2.1V

VCOMI_INT.CLP: 1.1V

Test condition: CCOMI[2.2uF], CVDD[10uF], CVDD[470uF], Lm[1mH].

Ch1[VDD],, Ch2[VIN], Ch3[VCOMI], Ch4[IOUT]

VCOMI_INT.CLP: 1.5V

22 Company Confidential

Test Results

Startup time

Startup time can meet 0.2s.

Test condition: Vin[90Vac], COUT[470uF], CCOMI[2.2uF], Lm[1mH]

Rstr: 30kΩ

178ms

Ch1[VDD],, Ch2[VIN], Ch3[VOUT], Ch4[IOUT]

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