CMOS VLSI Design - eas.uccs.educwang/ECE4340/Chapter1_2.pdf · 1 CMOS VLSI Design Circuits & Layout...
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1 CMOS VLSI Design Circuits & Layout Slide 2 CMOS VLSI Design Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams
Transcript of CMOS VLSI Design - eas.uccs.educwang/ECE4340/Chapter1_2.pdf · 1 CMOS VLSI Design Circuits & Layout...
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CMOS VLSIDesign
Circuits & Layout
Slide 2CMOS VLSI Design
OutlineA Brief HistoryCMOS Gate DesignPass TransistorsCMOS Latches & Flip-FlopsStandard Cell LayoutsStick Diagrams
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Slide 3CMOS VLSI Design
A Brief History1958: First integrated circuit– Flip-flop using two transistors– Built by Jack Kilby at Texas Instruments
2003– Intel Pentium 4 μprocessor (55 million transistors)– 512 Mbit DRAM (> 0.5 billion transistors)
53% compound annual growth rate over 45 years– No other technology has grown so fast so long
Driven by miniaturization of transistors– Smaller is cheaper, faster, lower in power!– Revolutionary effects on society
Slide 4CMOS VLSI Design
Annual Sales1018 transistors manufactured in 2003– 100 million for every human on the planet
0
50
100
150
200
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year
Global S
emiconductor B
illings(B
illions of US
$)
3
Slide 5CMOS VLSI Design
Invention of the TransistorVacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable1947: first point contact transistor– John Bardeen and Walter Brattain at Bell Labs– Read Crystal Fire
by Riordan, Hoddeson
Slide 6CMOS VLSI Design
Transistor TypesBipolar transistors– npn or pnp silicon structure– Small current into very thin base layer controls
large currents between emitter and collector– Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors– nMOS and pMOS MOSFETS– Voltage applied to insulated gate controls current
between source and drain– Low power allows very high integration
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Slide 7CMOS VLSI Design
1970’s processes usually had only nMOS transistors– Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit μProc
Slide 8CMOS VLSI Design
Moore’s Law1965: Gordon Moore plotted transistor on each chip– Fit straight line on semilog scale– Transistor counts have doubled every 26 months
Year
Transistors
40048008
8080
8086
80286Intel386
Intel486Pentium
Pentium ProPentium II
Pentium IIIPentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
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Slide 9CMOS VLSI Design
CorollariesMany other factors grow exponentially – Ex: clock frequency, processor performance
Year
1
10
100
1,000
10,000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro/II/III
Pentium 4
Clock S
peed (MH
z)
Slide 10CMOS VLSI Design
CMOS Gate DesignActivity:– Sketch a 4-input CMOS NAND gate
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Slide 11CMOS VLSI Design
CMOS Gate DesignActivity:– Sketch a 4-input CMOS NOR gate
A
B
C
DY
Slide 12CMOS VLSI Design
Complementary CMOSComplementary CMOS logic gates– nMOS pull-down network– pMOS pull-up network– a.k.a. static CMOS
pMOSpull-upnetwork
outputinputs
nMOSpull-downnetwork
X 0Pull-down ON
1Z (float)Pull-down OFFPull-up ONPull-up OFF
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Slide 13CMOS VLSI Design
Series and ParallelnMOS: 1 = ONpMOS: 0 = ONSeries: both must be ONParallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
Slide 14CMOS VLSI Design
Conduction ComplementComplementary CMOS gates always produce 0 or 1Ex: NAND gate– Series nMOS: Y=0 when both inputs are 1– Thus Y=1 when either input is 0– Requires parallel pMOS
Rule of Conduction Complements– Pull-up network is complement of pull-down– Parallel -> series, series -> parallel
A
B
Y
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Slide 15CMOS VLSI Design
Compound GatesCompound gates can do any inverting functionEx: (AND-AND-OR-INVERT, AOI22)Y A B C D= +
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
pMOS network
nMOS network
Slide 16CMOS VLSI Design
Example: O3AI( )Y A B C D= + +
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Slide 17CMOS VLSI Design
Example: O3AI ( )Y A B C D= + +
A B
Y
C
D
DC
B
A
Slide 18CMOS VLSI Design
Signal StrengthStrength of signal– How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0nMOS pass strong 0– But degraded or weak 1
pMOS pass strong 1– But degraded or weak 0
Thus nMOS are best for pull-down network
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Slide 19CMOS VLSI Design
Pass TransistorsTransistors can be used as switches
g
s d
g
s d
Slide 20CMOS VLSI Design
Pass TransistorsTransistors can be used as switches
g
s d
g = 0s d
g = 1s d
0 strong 0Input Output
1 degraded 1
g
s d
g = 0s d
g = 1s d
0 degraded 0Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
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Slide 21CMOS VLSI Design
Transmission GatesPass transistors produce degraded outputsTransmission gates pass both 0 and 1 well
Slide 22CMOS VLSI Design
Transmission GatesPass transistors produce degraded outputsTransmission gates pass both 0 and 1 well
g = 0, gb = 1a b
g = 1, gb = 0a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a bg
gb
a bg
gb
a bg
gb
g = 1, gb = 0
g = 1, gb = 0
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Slide 23CMOS VLSI Design
TristatesTristate buffer produces Z when not enabled
11011000
YAEN
A Y
EN
A Y
EN
EN
Slide 24CMOS VLSI Design
TristatesTristate buffer produces Z when not enabled
111001Z10Z00YAEN
A Y
EN
A Y
EN
EN
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Slide 25CMOS VLSI Design
Nonrestoring TristateTransmission gate acts as tristate buffer– Only two transistors– But nonrestoring, i.e., the output Y is not driven
by Vdd or GND• Noise on A is passed on to Y
A Y
EN
EN
Slide 26CMOS VLSI Design
Tristate InverterTristate inverter produces restored output– Violates conduction complement rule– Because we want a Z output
A
YEN
EN
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Slide 27CMOS VLSI Design
Tristate InverterTristate inverter produces restored output– Violates conduction complement rule– Because we want a Z output
A
YEN
A
Y
EN = 0Y = 'Z'
Y
EN = 1Y = A
A
EN
Slide 28CMOS VLSI Design
Multiplexers2:1 multiplexer chooses between two inputs
X11
X01
1X0
0X0
YD0D1S
0
1
S
D0
D1Y
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Slide 29CMOS VLSI Design
Multiplexers2:1 multiplexer chooses between two inputs
1X11
0X01
11X0
00X0
YD0D1S
0
1
S
D0
D1Y
Slide 30CMOS VLSI Design
Gate-Level Mux Design
How many transistors are needed?1 0 (too many transistors)Y SD SD= +
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Slide 31CMOS VLSI Design
Gate-Level Mux Design
How many transistors are needed? 201 0 (too many transistors)Y SD SD= +
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D1
D0S Y
4
2
22 Y
2
D1
D0S
Slide 32CMOS VLSI Design
Transmission Gate MuxNonrestoring mux uses two transmission gates
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Slide 33CMOS VLSI Design
Transmission Gate MuxNonrestoring mux uses two transmission gates– Only 4 transistors
S
S
D0
D1YS
Slide 34CMOS VLSI Design
Inverting MuxInverting multiplexer– Use compound AOI22– Or pair of tristate inverters– Essentially the same thing
Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1Y
0
1S
Y
D0
D1
S
S
S
S
S
S
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Slide 35CMOS VLSI Design
D LatchWhen CLK = 1, latch is transparent– D flows through to Q like a buffer
When CLK = 0, the latch is opaque– Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latc
h D
CLK
Q
Slide 36CMOS VLSI Design
D Latch DesignMultiplexer chooses D or old Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
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Slide 37CMOS VLSI Design
D Latch Operation
CLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q
Slide 38CMOS VLSI Design
D Flip-flopWhen CLK rises, D is copied to QAt all other times, Q holds its valuea.k.a. positive edge-triggered flip-flop, master-slave flip-flop
Flop
CLK
D Q
D
CLK
Q
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Slide 39CMOS VLSI Design
D Flip-flop DesignBuilt from master and slave D latches
QMCLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latc
h
Latc
h
D QQM
CLK
CLK
Slide 40CMOS VLSI Design
D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QMQ
D
CLK
Q
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Slide 41CMOS VLSI Design
Race ConditionBack-to-back flops can malfunction from clock skew– Second flip-flop
• fires late (if no clock skew, CLK1 and CLK2 should arrive at the the same time)
• sees first flip-flop change and captures its result– Called hold-time failure or race condition
CLK1
D Q1
Flop
Flop
CLK2
Q2
CLK1
CLK2
Q1
Q2
Slide 42CMOS VLSI Design
Nonoverlapping ClocksNonoverlapping clocks can prevent races– As long as nonoverlap exceeds clock skew– Industry manages skew more carefully instead
φ1
φ1φ1
φ1
φ2
φ2φ2
φ2
φ2
φ1
QMQD
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Slide 43CMOS VLSI Design
Gate LayoutLayout can be very time consuming– Design gates to fit together nicely– Build a library of standard cells
Standard cell design methodology– VDD and GND should abut (standard height) and
often called supply rails– Adjacent gates should satisfy design rules– nMOS at bottom and pMOS at top– All gates include well and substrate contacts
Slide 44CMOS VLSI Design
Example: Inverter
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Slide 45CMOS VLSI Design
Example: NAND3Horizontal N-diffusion and p-diffusion stripsVertical polysilicon gatesMetal1 VDD rail at topMetal1 GND rail at bottom32 λ by 40 λ
Slide 46CMOS VLSI Design
Stick DiagramsStick diagrams help plan layout quickly– Need not be to scale– Draw with color pencils or dry-erase markers
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Slide 47CMOS VLSI Design
Wiring TracksA wiring track is the space required for a wire– 4 λ width, 4 λ spacing from neighbor = 8 λ pitch
Transistors also consume one wiring track
Slide 48CMOS VLSI Design
Well spacingWells must surround transistors by 6 λ– Implies 12 λ between opposite transistor flavors– Leaves room for one wire track
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Slide 49CMOS VLSI Design
Area EstimationEstimate area by counting wiring tracks– Multiply by 8 to express in λ
Slide 50CMOS VLSI Design
Example: O3AISketch a stick diagram for O3AI and estimate area– ( )Y A B C D= + +
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Slide 51CMOS VLSI Design
Example: O3AISketch a stick diagram for O3AI and estimate area– ( )Y A B C D= + +
Slide 52CMOS VLSI Design
Example: O3AISketch a stick diagram for O3AI and estimate area– ( )Y A B C D= + +
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Slide 53CMOS VLSI Design
HW#2Due: September 11 class timeNo late homework acceptedExercises: 1.8, 1.9, 1.11, 1.12, 1.18
