Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of...

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10/27/2004 09 frequency domain 1 TUE/EE 5DD17 netwerk analyse 04/05 - © NvdM Clock Degradation and AC Steady State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state, the output is also sinusoidal We will introduce techniques that allow to solve for steady-state behavior without using DE’s These techniques resemble ordinary DC analysis, but use complex arithmetic Also introduce RMS value of signals (§ 9.4) § 9.4 Application: clock-signal degradation by interconnect network Use superposition and Fourier series (Ch. 7)

Transcript of Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of...

Page 1: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

10/27/2004 09 frequency domain 1TUE/EE 5DD17 netwerk analyse 04/05 - © NvdM

Clock Degradation and AC Steady State Analysis

Ch. 8

AC steady state analysis of RLC circuitsCkts are driven by sinusoidal sources (sin(ωt), cos(ωt))In steady-state, the output is also sinusoidalWe will introduce techniques that allow to solve for steady-state behavior without using DE’sThese techniques resemble ordinary DC analysis, but use complex arithmetic

Also introduce RMS value of signals (§ 9.4)

§ 9.4

Application: clock-signal degradation by interconnect network

Use superposition and Fourier series (Ch. 7)

Page 2: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Sinusoidal Signals

§ 8.2.1

( )ϕω += tVtv cos)(

Sinusoidal signals are fully specified with

Phase angleϕ

Radian frequency (T = Periodicity)ω=2π/TAmplitudeV

cos –sin

Many convenient relations. Example:

( ) ( )tt ωω sinsin −=−

( ) ( )tt ωω coscos =−

( )tt ωπω sin2

cos −=⎟⎠⎞

⎜⎝⎛ +

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Phase Relations

( ) ( )Rtitv =

R

+ -v(t)

i(t)

Are voltage and current in phase ?

( ) ( )ϕω += tIti cos ( ) ( )ϕω += tRItv cos YES for a resistor

L

v(t)

i(t)

+ -( ) ( )

dttdiLtv =

( ) ( )ϕω += tIti cos ( ) ( )ϕωω +−= tLItv sin ⎟⎠⎞

⎜⎝⎛ ++=

2cos πϕωω tLI

NO for an inductor

( )tt ωπω sin2

cos −=⎟⎠⎞

⎜⎝⎛ +( ) ( )tt

dtd ωωω sincos −= ( ) ⎟

⎠⎞

⎜⎝⎛ +=

2coscos πωωω tt

dtd

Expl 8.1

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C

+ -v(t)

i(t)( ) ( )

dttdvCti =

( ) ( )ϕω += tVtv cos ( ) ⎟⎠⎞

⎜⎝⎛ ++=

2cos πϕωω tCVti

NO for a capacitor

Capacitor Phase RelationsAre voltage and current in phase ?

Page 5: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Phase Relations Summary

I = ωCV cos (ωt + ϕ + π/2)V(cos (ωt + ϕ)C

V = ωLI cos (ωt + ϕ + π/2)I(cos (ωt + ϕ)L

V = RI cos (ωt + ϕ)I(cos (ωt + ϕ)R

Response (result quantity)Forcing function (applied quantity)

Resistor current and voltage are in phase

Inductor voltage leads (voorlopen) induction current by 90°

Capacitor current leads capacitor voltage by 90°

a leads b b lags a (achterlopen)

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Combination of Sinusoidal Sources

( )3020 −tcos ω ( )6040 +tcos ω ( ) ( )43.33cos72.44 +ω= ttv

=+ +– – +–

Result of adding two sinusoidal signals with same frequency is again a sinusoid with same frequency but with different phase

0 5 10 15-50

0

50v1v2v1+v2

Page 7: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Proof using Trigonometry (2)

( ) ( ) ( )60cos4030cos20 +ω+−ω= tttv

30sinsin2030coscos20 tt ω+ω= 60sinsin4060coscos40 tt ω−ω+

( ) ( ) tt ω−+ω+= sin60sin4030sin20cos60cos4030cos20tt ω−ω= sin64.24cos32.37

20 cos (ωt – 30) + 40 cos (ωt + 60) = 44.72 cos (ωt + 33.43)

Proof:

( ) vuvuvu sinsincoscoscos +=−

( ) uu sinsin −=−

Page 8: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Proof using Trigonometry (3)

24.64

37.32

44.72

43.3372.4432.37acos =⎟

⎠⎞

⎜⎝⎛

43.3372.4464.24asin =⎟

⎠⎞

⎜⎝⎛ ( )43.33sin

72.4464.24

=⇔

( ) tttv ωω sin64.24cos32.37 −=

( ) ⎟⎠⎞

⎜⎝⎛ −×= tttv ωω sin

72.4464.24cos

72.4432.3772.44

( )tt ω−ω= sin43.33sincos43.33cos72.44( ) vuvuvu sinsincoscoscos +=−

( ) ( )43.33cos72.44 += ttv ω

( )43.33cos72.4432.37

=⇔

( ) uu sinsin −=−

33.43

Page 9: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Proof using Trigonometry (4)

( ) ( ) ( )60cos4030cos20 +ω+−ω= tttv

30sinsin2030coscos20 tt ω+ω= 60sinsin4060coscos40 tt ω−ω+

( ) ( ) tt ω−+ω+= sin60sin4030sin20cos60cos4030cos20tt ω−ω= sin64.24cos32.37

( )43.33cos72.44 +ω= t

20 cos (ωt – 30) + 40 cos (ωt + 60) = 44.72 cos (ωt + 33.43)

Proof:

0 5 10 15-50

0

50v1v2v1+v2

Q.E.D.

Page 10: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Review

Result of adding two sinusoidal signals with same frequency is again a sinusoid with same frequency but with different phase

Procedure of adding sinusoidal signal using trigonometrypossible, but requires some ingenuity

Will not elegantly solve our general problem

First, we will review polar form of complex numbers

Then we are ready for phasor concept

20 cos (ωt – 30) + 40 cos (ωt + 60) = 44.72 cos (ωt + 33.43)

Page 11: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Polar Form and Angle Notation

jb

Im

Reaθ

r

A = a + jb θ = angle, or argument= arg A

r = amplitude, or magnitude= |A|

22 bar +=

abatan=θ

a = r cosθ

b = r sinθ

A = a + jb = r cosθ + jr sinθ = r (cosθ + j sinθ )= r ejθ (Eulers Identity)

A = a + jb = r ejθ ≡ r∠θ

Polar form Angle notation

Page 12: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Only Magnitude and Phase20 cos (ωt – 30) + 40 cos (ωt + 60) = 44.72 cos (ωt + 33.43)

Addition of sinusoidal signals with same frequency is again a sinusoid with same frequency but with different phase

same frequency but different phase and amplitude

Conclusion: for analysis of time-invariant linear systems driven by sinusoidal signals of a given frequency ω, we only need to explicitly work with amplitude and phase

In general: a linear time invariant network can’t change the frequency of a signal, only the phase and amplitude

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Phasors

amplitude and phase differenceare the principal concernsconvenient representation:vectors rotating atconstant angular velocity ω

lengths = amplitudesangles = phase differences

conventions:counterclockwise rotationprojection on x-axis

phasor diagram issnapshot of the rotatingconfiguration

From wisselstroomtheorie (Otten)

( )tjIe ω

Page 14: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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From wisselstroomtheorie (Otten)

Also see Figure 8.3

( )tjIe ω

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PhasorsThus: we only need to focus on magnitude and phase

These can be represented as one complex numberIm

Re

magnitude V

phase ϕ

( ) ( )ϕω += tVtv cos

( )ϕω= jtj VeeRe

( )ϕ∠= ω Ve tjRe

( ) ϕϕω ∠⇒+ VtcosV Phasor Transform

( ) ( )ϕωϕ ωϕ +=⇒∠ tVeVeV tjj cosRe Inverse Phasor transform

Because frequency does not change, we can eliminate it from the notation, using it only implicitly and put it back later after all calculations ( ) ( ) ϕϕϕω ω ∠⇒∠=+ VVetV tjRecos

Rotating vector

( )( )ϕω += tjVeRe

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Phasor vs Polar Form and Complex Arithmetic

A phasor V∠ϕ is like a polar form number A∠θ, but is implicitly associated with a frequency ω

Otherwise, it is a complex number and obeys all rules of complex arithmetic. Examples:

( )ϕθϕθ +∠⋅=∠⋅∠ baba

( )ϕθϕθ −∠=∠∠ b/ab/a

=∠+∠ ϕθ ba( )ϕθϕθ sinsincoscos bajba +++=

( ) ( )22 sinsincoscos ϕθϕθ baba +++= ⎟⎠

⎞⎜⎝

⎛++

∠ϕθϕθ

coscossinsinatan

bba

ϕϕθθ sincossincos jbbjaa +++

Addition requires rectangular coordinatesr∠θ = a + jb22 bar +=

abatan=θ

22 bar +=

abatan=θ

a = r cosθ

b = r sinθ

a = r cosθ

b = r sinθ

1.

2.

3.

Page 17: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Example1 : Proof using Phasors

( ) ( ) ( )60cos4030cos20 +ω+−ω= tttv

20 cos (ωt – 30) + 40 cos (ωt + 60) = 44.72 cos (ωt + 33.43)

Proof using phasors (see example 8.3):

to frequency domain

60403020 ∠+−∠=V

( ) ( ) 60sin4060cos4030sin2030cos20 jj ++−+−=

jj 64.34201032.17 ++−=

43.3372.44 ∠=

( ) ( )tjj eetv ω43.3372.44Re=

back to time domain

( )43.33cos72.44 += tω

j.. 64243237 +=

3.(Use from previous slide)

...=V extra bold font for phasors...=V extra bold font for phasors

Q.E.D.

Page 18: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Example 2: Phase Relations Using Phasors

Multiplication by j is rotation in complex plane by 2π

(because ( ) ( ) ( )2121 argargarg zzzz +=× )

V Iπ/2 Current lags voltage

Voltage leads current

⇒ Voltage leads current by π/2

Three ‘phasor’ ways to illustrate I-V phase relation (of inductor)

tjj eIedtdL

dtdL ωϕ== IV ILjω=

( ) ( )ϕω += tIti cos

ϕωϕ ∠== IeIe tjjI

Inductance:

1.

Page 19: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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ϕπω jj IeLe ⋅= 2

Inverse Phasor Transform (back to time domain)

( )⎟⎟⎟

⎜⎜⎜

⎛=

⎥⎦⎤

⎢⎣⎡ +⎟

⎠⎞

⎜⎝⎛ + tj

LIetvωπϕ

ω 2Re

⎟⎠⎞

⎜⎝⎛

⎟⎠⎞

⎜⎝⎛ +++⎟

⎠⎞

⎜⎝⎛ ++=

2sin

2cosRe πϕωπϕωω tjtLI

= ωLI cos (ωt + ϕ + π/2)

IV Ljω=

⎟⎠⎞

⎜⎝⎛ +

⋅= 2πϕ

ωj

IeL ⎟⎠⎞

⎜⎝⎛ +∠=

2πϕωLI

2.

3.

⇒ Voltage leads current by π/2

Example 2: Phase Relations Using Phasors

⇒ Voltage leads current by π/2

ϕϕ jIeI =∠=I ⇒

ϕωθ jIeLjV ⋅=∠

Page 20: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Impedance

Ohms law defines resistance( ) ( )Rtitv =

Capacitor relates current and voltage through differential equation

( ) ( )dt

tdvCti =

In the frequency domain, we will find

IV Z=Z is called the impedance of the capacitor

Impedance is defined as the ratio of the voltage and current phasors

(Complex) impedances and phasors allow frequency domain solution of RLC circuits as if they are R circuits, by using complex arithmetic. Avoid D.E.’s

§8.3

Page 21: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Impedance of a Capacitor

tjj eVedtdC ωϕ= tjj eVeCj ωϕω= VCjω=

The (complex) impedance of a capacitor is given byCj

CjZ

ω−

=1

VIdtdC=

IVCjω

=1⇒

CjZ

ω=

1⇒

How can we compute Z?tjj eVeV ωϕϕ =∠=V

C

I+

-V

ϕ∠= VV

IV Z=

frequency domain

θ∠= II

V

C

i(t)+

-v(t)

( ) ( )ϕω += tVtv cos

( ) ( )dt

tdvCti =

time domain

Page 22: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Impedance of an Inductor

I+

-V

ϕ∠= II

i(t)+

-v(t)

( ) ( )ϕω += tIti cos

tjj eIedtdL

dtdL ωϕ== IV

ILjω=

The impedance of an inductor is given by Z = jωL

Page 23: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Impedance, Resistance, Reactance

C1j

Cj1Z

LjZ RZ

ω−=

ω=

ω==

jXRZ +=R is the resistance

X>0 : X is the inductive reactance

X<0 : X is the capacitive reactance

impedance is a complex number equal to the ratio of the phasor voltage and the phasor currentmeasured at the same port (terminal pair)

X is the reactance

From wisselstroomtheorie (Otten)

Page 24: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Admittance, Conductance, Susceptanceadmittance is reciprocal impedance: a complex number equal to the ratio of the phasor current and the phasor voltage measured at the same port (terminal pair)

L1j

Lj1Y

CjY R1Y

ω−=

ω=

ω=

=

jBGY +=G is the conductance

X is the susceptanceX>0 : X is the capacitive susceptance

X<0 : X is the inductive susceptance

From wisselstroomtheorie (Otten)

Page 25: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Circuit Simplification

Now we know impedance of R, C, L

Can we also determine impedance of series and parallel connections?

YES: circuit simplification works!

KVL and KCL are also true in frequency domain

V1 V2+ +- -I

+ -

VZ1 Z2

V+ -

Zeq

I

V1 = I Z1 V2 = I Z2 V = I Zeq Zeq = Z1 + Z2

§8.3.2-8.3.3

(Complex) impedances and phasors allow frequency domain solution of RLC circuits as if they are R circuits, by using complex arithmetic. Avoid D.E.’s

Page 26: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Example: Simplification of Series RC

+ -

Ri(t)C

v(t)

R

+ -

V

I Z

+ -V

I

IV ⎟⎠

⎞⎜⎝

⎛+=

CjR

ω1

RCCR

ω−

∠ω

+=1atan1

222

Cj

ω−

R

Cjω1

I⎟⎠⎞

⎜⎝⎛

ω−

+=CjR

z

IZ=

CjRZ

ω−

+= ⎟⎠⎞

⎜⎝⎛ −

=RCω

θ 1atan

Page 27: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Impedance is not a Phasor

RCCR

ω−

∠ω

+=1atan1

222

Z has a magnitude and angle (argument)Can also be written in polar form and with angle notationBut it is NOT A PHASOR --- just a complex quantityBecause there is not an implicit frequency (angle is not phase)Even if Z is frequency dependent

CjRZ

ω−

+= θ∠= Z

Page 28: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Simplification of Parallel Circuits

R L

+

-V

I

R jωL

+

-V

I

Z1

+

-V

I

Z2

1ZVI1 =

22 Z

VI =

eqZV

=

∑=i ieq ZZ

11∑=i

ieq YY

Zeq

+

-V

I

RVI1 =

Ljω=

VI2

LjR ω+=

VVIeqZV

=

LjRZY

eqeq ω

+==111

LjRLRjZeq ω+

ω=

21 ZZVVIII 21 +=+=

KCL

Page 29: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Determine vc(t) when vs(t) = V cosωt ⇔ V∠0

Plan: determine I and multiply by impedance of C

τ

⎟⎠⎞

⎜⎝⎛ωτ−

∠ω

π−∠=

1atan120

222

CRC

V

+

-vs C

R

vc

+

-vs C

R

vc

+

-V C

R

VcI

+

-V C

R

VcI

+

-V C

R

VcI

Frequency Domain Circuit Analysis Example

211 π

−∠ω⋅=

ω⋅=

CCjIIVc

⎟⎠⎞

⎜⎝⎛ω−

∠ω

+

∠==

RCCR

V1atan1

0

222Z

VIZ

Page 30: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Back to Time Domain

⎟⎠⎞

⎜⎝⎛ωτ−

−π

−∠+τω

=1atan

2122V

( ) ( )θωτω

++

= tVtvc cos122 2

1atan π−⎟

⎠⎞

⎜⎝⎛ωτ

Amplitude depends on frequency

(Phase-shift too)

More on this later...

⎟⎠⎞

⎜⎝⎛ωτ−

∠ω

π−∠=

1atan12

222

CRC

VCV ( ) ( )αα −−= atanatan

atan has odd symmetry

21atan

122π

−⎟⎠⎞

⎜⎝⎛ωτ

∠+τω

=V

Page 31: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Intermezzo

+

-vs C

R

vc

+

-vs C

R

vc

+

-V C

R

VcI

+

-V C

R

VcI

+

-V C

R

VcI

We have

21atan

122π

−⎟⎠⎞

⎜⎝⎛ωτ

∠+τω

=VVc

Book (example 8.6) has

ωττω

atan122

−∠+

=VVc

Hence -atanωτ should equal2

1atan π−⎟

⎠⎞

⎜⎝⎛ωτ

Proof on next slide

Page 32: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Proof

Show that 2

1atanatan π−=−

xx

x1tan =ϕ ϕ=

x1atan

x−=⎟⎠⎞

⎜⎝⎛ π

−ϕ2

tan

( )2

atanatan πϕ −=−=− xx

Q.E.D.

21atan π−=

x

ϕ

x

1

1

-x

π/2

( )xx −=− atanatan

Page 33: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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V

R VC ?I

Cjω1

V

R VC ?I

Cjω1

AC steady state

VC?

V

I

Resistive Circuits versus Phasor CircuitsDC

( )21 RRVI +=

21

221 RR

RVRIV+

⋅=⋅=

⎟⎠

⎞⎜⎝

⎛+=

CjR

ω1VI

RCjRCj Cj

Cjω+

=+

⋅=ω

⋅=ω

ω

11

1

1VVIVc

You should really see clearly that procedure from previous slides (e.g. determine I and multiply by impedance) is just the same as shown here --- just use complex arithmeticAnd you should be able to apply such techniques on the exam(with numbers it might be easier)

V

R1 V1 ?

R2

I

V

R1 V1 ?

R2R2

I

Page 34: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Example of Circuit Simplification (1)

+

-40∠0

-j3

9

j3

-j19

10

1 0.2 j0.6 V0

Determine V0 phasor, using source transformation techniques

Frequency not explicitly specified, but is implicitly given in impedance of elements

Plan:

1. Eliminate left-most loop by replacing it by Thévenin equivalent

2. Compute current through circuit

3. Multiply current by impedance of right-most branch

Page 35: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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+

-40∠0

-j3

9

j3

-j19

10

1 0.2 j0.6 V0

3140

jI

+=

Determine V0 phasor, using source transformation techniques

22))((

))(())((

dcdjcbja

djcdjcdjcbja

djcbja

+

−+=

−+−+

=++

Example of Circuit Simplification (2)

124)31(1040 jj −=−=

4 - -j3

9j3

-j19

10

1

0.2 j0.6

j12

V0

I

Page 36: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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4 - -j3

9j3

-j19

10

1

0.2 j0.6

j12

V0

10)39)(31( jjZ −+

=

4 - 1.8+j2.4-j19

10

0.2 j0.6

j12

V0

Z

241892739)39)(31( 2 jjjjjj +=−+−=−+

Example of Circuit Simplification (3)

4.28.1 j+=

Page 37: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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4 - -j3

9j3

-j19

10

1

0.2 j0.6

j12

V0

10)39)(31( jjZ −+

=

4 --j19

10

0.2 j0.6

j12

V0

Z

241892739)39)(31( 2 jjjjjj +=−+−=−+

Example of Circuit Simplification (3)

4.28.1 j+=

1.8+j2.4

Page 38: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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4 - 1.8+j2.4-j19

10

0.2 j0.6

j12

V0

08.156.125

2739)43(4)13(12

16121236 jj

jj

jjI +=

+=

−−

=−−

=

1236)4.28.1)(124( jjjV −=+−=

84.1812.36)1910)(08.156.1(0 jjjV −=−+=

36-j12

1.8+j2.4

-j19

10

0.2 j0.6

+

-

V0

IV

74.4084.1812.36 22 =+ °−=− 55.27

12.3684.18atan

°−∠= 55.2774.40

Example of Circuit Simplification (4)

Page 39: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Note

+

-40∠0

-j3

9

j31

36-j12

1.8+j2.4

+

-

We had replaced circuit on the left by equivalent on the right

This is only valid for a specific frequency

For that frequency, we cannot distinguish circuits by looking (measuring) at its ports

Other frequencies would require/produce other equivalent circuits!

But calculation procedure remains the same!

Page 40: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Resonance°−∠= 55.2774.400V

+

-40∠0

-j3

9

j3

-j19

10

1 0.2 j0.6 V0

Note: |V0| > 40Seems impossible: output voltage exceeds source voltageBut it is correct, this phenomenon is called resonance(R)LC circuits driven by sinusoidal signals can exhibit resonance: Output voltage can peak because of interaction between energy stored and released in L and C elements when damping factor is low.See § 8.6 (and Figure 8.23 in particular)

Resonance! (§ 8.6)

RLC-exercises can have answers with voltages exceeding those of any (or even the sum) of the sources!

Page 41: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Complete response = transient + steady-statetransient (natural response) always dies outsteady-state (forced response) is what remains

AC Steady-state solution is our current goalAlways has same frequency as source signalSinusoidal sources => sinusoidal responses with same frequency ( ) ( )xxx tVtv ϕω += cos ( ) ( )yyy tIti ϕω += cosω is known from the start, need only compute magnitudes and phases (e.g. Vx and ϕx) Phasors

Analyze circuits with one or more sinusoidal sources

( ) ( )ϕω += tVtv ms cos [V]Vm = amplitude, or magnitude [V]ω = 2πf = frequency [rad/s] ϕ = phase angle [degree]

Frequency Domain Analysis Summary

Page 42: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Phasors are complex numbers representing magnitude and phase, implicitly associated with (source) frequency

Phasors allow frequency domain representation and analysis of circuit

R R C Cj

Cj ω−

=ω1

L Ljω

(Time domain) differential equations become (frequency domain) algebraic equationsSolve RLC circuits like resistive circuits (but use complex arithmetic)

(use either technique: node voltage method, mesh current, voltage and current division source transformation, series/parallel simplification , Thévenin/Norton equivalents, superposition, and so on)

Return to time domain by using inverse phasor transform

( ) ( )xxtj Qetq ϕ∠= ωRe (q(t) is unknown quantity, current

or voltage)

Frequency Domain Analysis Summary

Page 43: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Effective ‘value’ of Time-Varying Signals

Peak – to – peak value 2V?No: does not distinguish between waveforms (same for all those above)Average value? No: is zero for symmetric waveforms like these.

§9.4

What is a good measure (maat) for voltage / strength / size / effectiveness of time varying signal?

-V

V

t-V

V

t

-V

V

t

V

-Vt

Page 44: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Root–Mean–Square Value

Effective voltage relative to power delivered to a resistive load

DC: V = I R RIR

VVIP 22===

Time - Varying

( ) ( )∫=T

dttitvT

P0

1 Average Power

( )∫=T

dttvTR 0

211

2EFFV

RVP EFF

2= ( )∫=≡

TRMSEFF dttv

TVV

0

21

The Root-Mean-Square (RMS) value of a signal is that value that would deliver the same power to a resistive load as a DC signal with same voltage

root

meansquare

Page 45: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Root – Mean – Square Value

The RMS value of a signal (time varying voltage or current) is with respect to dissipation equivalent to the same DC value

RVP RMS

2= ( )∫=

TRMS dttv

TV

0

21

RIP RMS2= ( )∫=

TRMS dtti

TI

0

21

Integrate over representative time interval

One period (or integer multiple)

Or ‘sufficiently long’

A multi-meter shows RMS value

Mains electricity is 220V RMS

RMS is standard way of specifying AC signal/sources (unless otherwise noted)

Page 46: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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RMS Example

( )⎥⎥

⎢⎢

⎡∫ −+∫=T

T

T

RMS dtVdtVT

V2

22

0

22 1

VVRMS =

( )∫=2

0

22 21TRMS dtV

TV

-V

+V

0 T t

VVRMS 2=

Compute VRMS

22V=[ ]TTV T 2

0

24=∫=∫=

TTdt

TVdtV

T 0

2

0

2 11 [ ] 20

2VT

TV T ==

2xV

0 T t

Same signal, but shifted along V-axis. Do you expect VRMS to be equal, larger or smaller than on the left?

Page 47: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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RMS Value of Sinusoidal SourcesV

-V

VVRMS 21

= (See book)

The RMS value of a sinusoidal source is 0.707 times the amplitude

Page 48: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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RMS Value of Fourier Series Sources( )[ ]∫ ∑ θ+ω+=

TnnRMS dttnAA

TV

0

20 cos1

( ) ( )( )...2cos1cos 210 +θ+ω+θ+ω+ nn tAtAA

( ) ( )( )...2cos1cos 210 +θ+ω+θ+ω+× nn tAtAA

Again a signal with period T, integral will vanish (cosα cosβ =...)

Several kinds of terms

A20

When integrated, gives constant contribution

( )nn tnAA θ+ω× cos0

( ) ( )kknn tkAtnA θ+ω×θ+ω coscos

Integral of cosine over (multiple) complete period(s) will vanish

‘Rectified’ cosine wave, integral yields An

2/2( ) ( )nnnn tnAtnA θ+ω×θ+ω coscos

∑+=∞

=1

220 2n

nAA

Page 49: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Filtering

Amplitude and phase depend on frequencyCircuit principles like these are fundamental for filteringFiltering: selection of frequency rangesExamples: tuning of radio signals, filters in loudspeaker boxes(to separate signals for woofer and tweeter), ...Very central to Signal Processing, Radio Reception, …But currently very often done digitally (if frequency low enough)

( ) ( )θωτω

++

= tVtvc cos122 +

-V C

R

VcI

+

-V C

R

VcI

+

-V C

R

VcI

21atan πωτ

θ +⎟⎠⎞

⎜⎝⎛=

Next slides will peak-ahead to associated topics

Naturally, in the frequency domain§8.5

Page 50: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Transfer Function and Bode DiagramTransfer function ≡ Ratio of output phasor to input phasor

( )ωτ+

=≡ωjV

VcH1

1 ( ) ( ) ( )ωτ+−=ω≡ω jHH dB 1log20log20

Decibel: 20 times common logarithm (base 10) of signal strength

-20 dB

10 x frequency change

0-3

log(ω)

|H(ω)|DB

10

-10

-30

-20

-40-50

τ101

τ1

τ10

τ100

τ1000

high frequency asymptote

low frequency asymptote

half-power point

corner frequency

Page 51: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Transfer Function and Bode DiagramTransfer function ≡ Ratio of output phasor to input phasorDecibel: 20 times common logarithm (base 10) of signal strength

Also a standard plot for phase

We are not going to study this any further

But particularly good example of power of phasor analysis

0-3

log(ω)

|H(ω)|DB

10

-10

-30

-20

-40-50

τ101

τ1

τ10

τ100

τ1000

0-3

log(ω)

|H(ω)|DB

10

-10

-30

-20

-40-50

τ101

τ1

τ10

τ100

τ1000

0-3

log(ω)

|H(ω)|DB

10

-10

-30

-20

-40-50

τ101

τ1

τ10

τ100

τ1000

Page 52: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Overview/Conclusion

Phasor/frequency domain analysis (§8.1- §8.3)

Clock system analysis (§8.4) skipped, but we covered the tools

Preview of filtering and transfer functions (§8.5)

RLC Circuits in frequency domain skipped (§8.6)

Complex Fourier Series skipped (§8.7)

Root-Mean-Square values (§9.4)

Page 53: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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ExamWe have covered an introduction to Circuit Analysis

Exam will be on Fr 19/11/04, 2pm-5pm

All material (see next slides)

Indien het eind-tentamen >= 4.0:

Eindcijfer = max (eindtentamen, gemiddelde v. deeltentamen en eindtentamen)

If you have questions during preparation, you may contact me e.g. by e-mail: [email protected]

Keep on watching web site, I might put extra info on it. E.g. as a result of questions by some of you.

Page 54: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Contents

Fanout and capacitive couplingmore examples of circuits → ODE → solution

C4

Package inductance and RLC circuit analysis coupled ODE’swith non-real natural frequencies

C5

Interconnect and RC ladder circuitsCoupled ODE’s, natural frequencies

C3

Gate delay and RC circuitsFirst order RC circuits, linear first order ODETime response, energy, powe

C2

Fundamental conceptsCharge, current, voltage, powerCircuits, circuit elementsKirchoff laws

C1

Please make VERY sure that you can really fluently apply this!

Page 55: Clock Degradation and AC Steady State Analysis · State Analysis Ch. 8 AC steady state analysis of RLC circuits Ckts are driven by sinusoidal sources (sin(ωt), cos(ωt)) In steady-state,

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Contents (ctd)

Thévenin and Norton equivalent modelsControlled sourcesRoot-mean-square values Nodal analysis

S 9.1 – 9.5.1

Clock degradation and ac steady state analysisAlgebraic solution of circuitsPhasor representation(complex) impedance and admittance

S 8.1 – 8.3

Clock skew and signal representation Time domain vs frequency domain analysisSuperposition(7.6 only briefly)

S 7.1 – 7.7

Only one solution: invest your time and practice – practice – practice

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The End

Good luck, and thanks for your attention