1

CMOSDigital Integrated

CircuitsAnalysis and Design

Chapter 6 MOS Inverters: SwitchingCharacteristics and Interconnect Effects

2

Introduction • The parasitic capacitance

associated with MOSFET– Cgd, Cgs, gate overlap with diffusion– Cdb, Csb, voltage dependant junction

capacitance– Cg, the thin-oxide capacitance over

the gate area– Cint, the limped interconnect

capacitance– Load capacitance Cload= Cgd,n + Cgd,p

+ Cdb,n + Cdb,p + Cint + Cg• Csb,n and Csb,p have no effect on the

transient behavior of the circuit, since VSB=0

• The delay times calculated using Cload may slightly overestimate the actual inverter delay

– Charging, discharging

3

Delay-time definitions

( )

CDrise

ABfall

OLOHOL

OLOHOL

PLHPHLP

PLH

PHL

OLOHOLOHOL

tt

ttVVVVVVVV

tttt

VVVVVV

−=

−=−⋅+=−⋅+=

=

−=−=

+=−+=

+

τ

τ

τττ

ττ

9.0)(1.0

2

)(2/1)(2/1

%90

%10

23

01

%50

4

Calculation of delay time

• The simplest approach for calculating the propagation delay times τPHL and τPLH– Estimating the average capacitance current during

charge down and charge up–

– Not very accurate estimate of the delay time

)],(),([21

),(),([21

)(

)(

%50,

%50,

,

%50

,

,

%50

,

OLoutOLinCoutOLinCLHavg

outOHinCOHoutOHinCHLavg

LHavg

OLload

LHavg

LHloadPLH

HLavg

OHload

HLavg

HLloadPHL

VVVViVVVViI

VVVViVVVViI

IVVC

IVC

IVVC

IVC

==+===

==+===

−⋅=

∆⋅=

−⋅=

∆⋅=

τ

τ

5

Calculation of delay time(1)• The propagation delay times can be found more accurately by solving the state equation

of the output node in the time domain

( ) ( )

( )

( )

( )[ ] ( )[ ]

)]1)(4ln(2[)(

)1)(4ln(2[)(

)(2ln()(

))(2

ln()(2

12

)])(2[

1(2)1(

22

22

linear nMOS gConsiderin boundary.region linear -saturation at the be r will transisto theand is tageoutput vol the,At

2

21

for 22

0

off pMOS discharge, tostartingon nMOS theinverter CMOS afor caseinput -resing heconsider t weFirst,

,

,

,

,

,

,

,

,

%50

%50,

,11

,,11

%50

,

%50

, 2,,

1

1

22

1

2,

,0

'1

2,,

2,

2,,

,,

,'1

0

,

−−

+−−

=

−+−

+−−

=

−−−

=−

−−−−=−

==

=−= −−

−=−===

−≤−−=−−=

=

−=−⇒

−−=⎟

⎟⎠

⎞⎜⎜⎝

⎛−=

≤<−=−=

−=≈

⇒

−==

′

′

−′

−=

=

=

=

−=

=

∫ ∫∫

∫∫ ∫

DD

nTDD

nTDD

nT

nTDDn

loadPHL

OLOH

nTOH

nTOH

nT

nTOHn

loadPHL

nTOH

nTOHn

load

outnTOH

out

nTOHn

load

out

nTOHout

out

nTOHoutou

outoutnTnloadout

nDload

T,nOHoutoutoutT,nOHn

outoutT,ninn

D,n

T,nDD'

nTOHn

nTload

VVV

VV out

tt

tt

VVV

VVnTOHn

loadout

nDload

OHoutT,nOHnTOHn

nTinn

nD

D,nout

loadD,p

nDpDCout

load

VVV

VVV

VVkC

VVVV

VVV

VVkC

VVVV

VVkCtt

VVVV

VVkCtt

VVVVV

VVVVV dV

VVVVOHkCdV

iC

tttt dt

VVforVVVVVkVVVVki

)-V(Vtt

VVkVC

tt

dVVVk

CdVi

Cdt

VV-VVVVkVVki

idt

dV, Ci

iiidt

dVC

nTOHout

OHout

nTOHout

OHout

τ

τ

6

Example 6.1

7

Example 6.2

8

Calculation of delay time (2)

( )

( )

[ ]

22

22

%50

%50,

,,,

%50

, ,

,

,

,2

,,

,

,,

,

,

,

,

,

,

%50

,

,

,

,

2)()(

2)()(

)(||2ln||

)|,|(2||

|| )(||

)(

||for )()(||22

for |)(|2

above rises is tageoutput vol when the

linear enter and ,saturationin initially pMOS thenote ,)(

load chargingon pMOS off, nMOS low, high to from switches ageinput volt When the

for i.e. delays,n propagatio balancedfor conditions sufficient the

1|)|(4ln|||)|(

1|)|(2ln||

2|)|(

input risingfor event down -charge the toanalogous completely issition input tranfallingfor ecapacitanc loadoutput theofevent up-chargetheinverter, CMOSaIn

⎟⎠⎞

⎜⎝⎛+=

⎟⎠⎞

⎜⎝⎛+=

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛

−−−

+−−

=

⎥⎦

⎤⎢⎣

⎡ =−= ⎟⎟

⎠

⎞⎜⎜⎝

⎛+

−== ⎟⎟

⎠

⎞⎜⎜⎝

⎛=

−>−−−=

≤=

+

=

===⇒

=

⎥⎦

⎤⎢⎣

⎡−⎟

⎠⎞

⎜⎝⎛ −

+−

×−

=

⎥⎦

⎤⎢⎣

⎡−⎟

⎠⎞

⎜⎝⎛

−−−

+−−

×−−

=

∫∫

fPLHPLH

rPHLPHL

DD

DDloadT

loadT

OLDD

loadTloadn

loadPLH

out

loadTDDout loadD

outloadTDDout

OLout loadD

outloadPLH

loadTDDoutoutDDoutDDloadTloadn

loadD

T,loadDDoutloadTloadn

loadD

T,loadDD

outloadDout

load

pnnppnT,pT,n

PLHPHL

DD

pTDD

pTDD

PT

pTDDp

loadPLH

OH

pTOLOH

pTOLOH

PT

pTOLOHp

loadPLH

stepinputactual

stepinputactual

VVVVV

VVloadVTV

VkC

VVVVV lineari

dVVVVVV sati

dVC

VVVVVVVVki

V-VVVki

VV

Vidt

dVC

/µµ/Wor W k and kVV

ττ

VVV

VVV

VVkC

VVVVV

VVVV

VVVkC

τττ

τττ

τ

τ

τ

τ

9

Calculation of delay time (3)• Considering the input voltage waveform is not an ideal

(step) pulse waveform, but has finite rise and fall times– Using an empirical expression as 6.29, 6.30

• The former expression based on the gradual channel approximation– Can still be used for sub-micron MOS transistors with proper

parameter adjustments– Yet , the current driving capability of sub-micron transistors is

significantly reduced as a result of channel velocity saturation• (W/L)-ratio• In deep-sub-micron nMOS saturation current no longer∝(VGS-VT)2

– Isat=κWn(VGS-VT)– τPHL≈(CloadV50%)/Isat=[Cload(VDD/2)]/ κWn(VGS-VT)– The propagation delay has only a weak dependence od the power

supply– Better estimate can be obtain by using an accurate short-

channel MOSFET model

10

Inverter design with delay constrains• The load capacitance Cload consist of

– Intrinsic components parasitic drain capacitances which depend on transistor dimensions

– Extrinsic component interconnect/wiring capacitance and fan-out capacitance• If Cload mainly consists of extrinsic components, and if this overall load

capacitance can be estimated accurately and independently of the transistor dimensions

– Given a required (target) delay value of τ*PHL– The (W/L)-ratio can be found as

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ −

−+

−−=⎟

⎠⎞

⎜⎝⎛

∗ 1)(4ln2)(

,

,

,

, DD

nTDD

nTDD

nT

nTDDoxnPHL

load

n

n

VVV

VVV

VVCC

LW

µτ

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ −

−+

−−=⎟

⎠⎞

⎜⎝⎛

∗ 1|)|(4ln||

||2)(

,

,

,

, DD

pTDD

pTDD

pT

pTDDoxpPLH

load

p

p

VVV

VVV

VVCC

LW

µτ

11

Example 6.3

12

Inverter design with delay constrains

)2( )2(

)(2 where

:as expressed becan load capacitive totalThe)(2)(2)(

)(2)(2

:are ecapacitanc parasiticdrain The

analysis in the neglected be willC and C escapacitancdrain -to-gate small relatively The6.8 Fig.in layout simplified theCondering

gates stage-next in the dimensions device theoffunction a also is ecapacotancout -fan the),()()()()(

component intrinsic t theaccunt tha into take tohave Cload If

,,0,

,,0,

int,,,,0

0

int,,,,,,0,,0

,,,,0,

,,,,0,

pgd,ngd,

int,,,,

pjswdrainpjpeqp

njswdrainnjneqn

gpeqpjswneqnjswdrain

ppnnload

gpeqpjswdrainpneqnjswdrainndrainpeqpjpneqnjnload

peqpjswdrainppeqpjdrainppdb

neqnjswdrainnneqnjdrainnndb

g

pngppdbnndbppgdnngdload

CDCKCDCK

CCKCKCDWWC

CCKCDWKCDWDKCWKCWCKCDWKCDWC

KCDWKCDWC

CWWfCCWCWCWCWCC

+=+=

+++=++=

++++++=++=++=

⇒

=+++++=

+

ααα

ααα

13

Inverter design with delay constrains

( )

gint

limitPLH

limitPHL

,

,

,

,

,

,

,

,

00

,

,

,

,

0

,

,

,

,

0

C and C component, ecapacitanc extrinsic theoft independen is delay timen propagatio The.parameters related-ogyby technol dictated are which es,limit valu thesebeyond reduced benot can delay n propagatio The

,

lues,certain va beyonddelay upon influence dimishing a have willsdelay timen propagatio thereduce to Wpand Wn Increasing

ly.respective , and for solvingby (6.46b), and (6.46a) from calculated becan sconstraintdelay esesatisfy thr which transistopMOS theandr transistonMOS theof widthschannel minimum the and edelay valuet Given targ

1|)|(4ln||

||2|)|(

1)(4ln2)(

)( ,)(

: as defined be r transistothe

othereach toequal and fixedusually are and lengths channel that theNote

1|)|(4ln||

||2|)|(

1)(4ln2)(

:delayn propagatio The

⎟⎠⎞

⎜⎝⎛ +=+=

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ −

−+

−×⎟⎟⎠

⎞⎜⎜⎝

⎛−

=Γ

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ −

−+

−×⎟⎟⎠

⎞⎜⎜⎝

⎛−

=Γ

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛ ++Γ=⎟

⎠⎞

⎜⎝⎛ ++

Γ=

≡

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ −

−+

−×⎟⎟⎠

⎞⎜⎜⎝

⎛−

×⎟⎠⎞

⎜⎝⎛ ++

=

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ −

−+

+×⎟⎟⎠

⎞⎜⎜⎝

⎛−

×⎟⎠⎞

⎜⎝⎛ ++

=

pn

ppnn

pn

*PLH

*PHL

DD

PTDD

pTDD

PT

pTDDoxp

pp

DD

nTDD

nTDD

nT

nTDDoxn

nn

p

ppn

pPLHn

npnnPHL

n

p

pn

DD

pTDD

pTDD

pT

pTDDoxp

p

n

ppnnPLH

DD

nTDD

nTDD

nT

nTDDoxn

n

n

ppnnPHL

αRαΓτRααΓτ

WWτ τ

VVV

VVV

VVCL

VVV

VVV

VVCLwhere

W

WR

WWR

WW

atio)R(aspect rioaspect rat

LLV

VVVV

VVVC

LW

WW

VVV

VVV

VVCL

WWW

µ

µ

ααατααατ

µααατ

µααατ

14

Example 6.4

15

Example 6.4

16

CMOS ring oscillator circuit• This circuit does not have a stable operating point• The only DC operating point:

– the input and output voltages of all inverters are equal to the logic threshold Vth(unstable)

• A closed-loop cascade connection of any odd number of inverter will display astable behavior

– will oscillate once any of the inverter input or output voltages deviate from the unstable operating point, Vth

– V1, VOL→VOH trigger V2 to fall, VOH→VOL, difference between the V50%-crossing times of V1 and V2, τPHL2 trigger V3 to rise, VOL→VOH, difference between the V50%-crossing times of V2 and V3, τPHL3......

– T= τPHL1+ τPHL1+τPHL2+ τPHL2+τPHL3+ τPHL3 =6τP– f=1/T=1/(2nτP), τP=1/2nf

17

Estimation of interconnect parasitics• The load

– Classical approach capacitive and lumped• Internal parasitic capacitance

of the transistor• Interconnect (line)

capacitances• Input capacitances of the fan-

out gates• Now, the interconnect line

itself– Three dimensional structure in

metal and/or polysilicon• Non-negligible resistance• The (length/width) ratio of the

wire distributed making the interconnect a true transmission line

• An interconnect is rarely isolated from other influence

18

Estimation of interconnect parasitics• If the time of flight across the interconnection line

is much shorter than the signal rise/fall times– The wire can be modeled as a capacitive load, or

as a lumped or distributed RC network• If the interconnection lines are sufficient long and

the rise times of the signal comparable to …– The inductance becomes important– Modeled as transmission lines–

– The longest wire on a VLSI chip (2cm) fright time≅133ps, shorter than rise/fall time capacitive or RC model

– 10 cm multi-chip module 1ns, the same order as rise/fall time considering RLCG

speedn propagatio theis and length, linect interconne theis Here,

modeling lumped 5)(

modeling lumpedor line-nsmissioneither tra

5)(5.2

modeling lineontransmissi 5.2)(

vlvl

vl

vl

vl

fallrise

fallrise

fallrise

⇒⎟⎠⎞

⎜⎝⎛×>

⎭⎬⎫

⎩⎨⎧

⇒⎟⎠⎞

⎜⎝⎛×<<⎟

⎠⎞

⎜⎝⎛×

−⇒⎟⎠⎞

⎜⎝⎛×<

ττ

ττ

ττ

19

The transmission line effect• IN CMOS VLSI chips

– Not serious concern– The gate delay due to capacitive load component dominated the line delay

• The sub-micron design rules– The intrinsic gate delay tend to decrease significantly– The overall chip size and the worse-case line length on a chip tend to increase

• Mainly due to increasing chip complexity• The widths of metal lines shrink while thickness increase

– The transmission line effects and signal coupling between neighboring lines become even more pronounced

• To optimize a system for speed, chip designer must have reliable and efficient means for

– Estimating the interconnect parasitics in a large chip– Simulating the transient effect

20

Interconnection delay

• The hierarchical structure of most VLSI design– Chip– Modules

• Inter-module connection longer

– Logic gates, transistors• Intra-module connection shorter

21

Interconnect capacitance estimation• A complicated task• Fringing-field factor FF=Ctotal/Cpp

22

Estimation of interconnection capacitance• The formulas provide accurate approximation of the

parasitic capacitance values to within 10% error, even for very small values of (w/h) and (t/h)– The linear dash-dotted line parallel-plate cap.– W/T decreases cap. Decreases

• Level off at approximately 1pF/cm, when the wire width is approximately equal to insulator thickness

2t w 47.1

22221ln

20543.01

2t w

22221ln

22

<

⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢

⎣

⎡

+

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛ +++

⎟⎠⎞

⎜⎝⎛ ⋅−

+=

≥

⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢

⎣

⎡

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛ +++

+⎟⎠⎞

⎜⎝⎛ −

=

for

th

th

th

ht

hwC

for

th

th

thh

twC

πε

πε

23

Capacitance coupling• Considering the

interconnection line is not completely isolated from the surrounding structures, but is coupled with other lines running in parallel– The total parasitic

capacitance increased by• Fringing-field effects• Capacitive coupling

between the lines– When the thickness of

the wire is comparable to its width coupling capacitance↑

– Signal crosstalk» Transitions in one

line can cause noise in the other lines

24

Capacitance of an interconnect line• The capacitance of a line which is coupled with two other lines on

both sides– If both of the neighboring lines are biased at ground potential– The total parasitic capacitance can be more than 20 times as large as the

simple parallel-plate capacitance

25

Capacitance between various layers

26

Interconnect resistance estimation• The total resistance

–

– The sheet resistivity• Polysilicon: 20-40 Ω/square• Silicided ploysilicon: 2-4 Ω/square• Aluminum: 0.1 Ω/square• Metal-poly, metal-diffusion contact: 20-30 Ω• Via resistance: 0.3 Ω

• We can estimate the total parasistic resistance of a wire segment based on its geometry– Short distance negligible– Long distance the total lumped resistance connect in series

with the total lumped capacitance

tρR

RwlR

twlR

sheet

sheet

sheetwire

=

Ω

⎟⎠⎞

⎜⎝⎛=

⋅⋅=

/square)( line theofy resistivitsheet the:

ρ

27

Calculation of interconnect delay- RC delay models• If the time of flight across the

interconnect line is significant shorter than the signal rise/fall times

– Can be modeled as a lumped RC network

– Assuming that the capacitance is discharged initially, and assuming that the input signal is a rising step pulse at time t=0

•

• Unfortunately, this simple lumped RC network provides a very rough approximation

• The accuracy of the simple lumped RC model can be significant improved by

– Dividing the total resistance into two equal parts

• More accuracy– RC ladder network

RC

RCVtV

RCtVtV

PLH

PLHDD

DDout

69.0 as found isnetwork RC lumped simple for thedelay n propagatio theand

exp1)(

at tpoint -50% thereaches tageoutput vol rising The

exp1)(

%50

PLH

≈

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛−−=

=

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎠⎞

⎜⎝⎛−−=

τ

τ

τ

28

Calculation of interconnect delay- The Elmore delay• Consider a general RC tree network

– There are no resistor loops in this circuit– All of the capacitors in an RC tree are connected between a node and a

ground– There is one input node in the circuit– There is a unique resistive path, from the input node to any other node

in the circuit• Path definitions

– Let Pi denote the unique path from the input node to node i, i=1,2,3..n– Let Pij=Pi∩Pj denote the portion of the path between the input and the

node i, which is common to the path between the input and node j

29

Calculation of interconnect delay- The Elmore delay( ) ( ) ( )

( ) ( ) ( ) ( )

( )

network RC lumped a of than that leconsiderab is line RC ddistribute a ofdelay n propagatio that thesee weThus,

for 2

21

21

and element identical of consisting network,ladder RC uniform a assume If

networkladder RC simplenetwork treeRC general theof case specificA

11

11

817161554214421321221115

8761776166151413121117

smaller

NRCN

NRCNNNR

NC

NR

NC

(C/N) (R/N)

RC

CRCRCRCRRRRCRRRCRRCRRCRCRRRCRRRCRRCRCRCRCRCR

DN

j

k

N

jDN

j

kk

N

jjDN

D

D

∞→=

+=

+⎟⎠⎞

⎜⎝⎛⎟⎠⎞

⎜⎝⎛==

=

⇒

++++++++++++++=++++++++++++=

∑∑

∑∑

==

==

τ

τ

τ

ττ

30

Example 5

31

Example 5

32

Switching power dissipation of CMOS inverters

( )

fVCP

VCT

P

VCCVVV

CT

P

dtdt

dVCVVdtdt

dVCVT

P

dttitvT

P

DDloadavg

DDloadavg

T

ToutloadloadoutDD

T

loadavg

T

Tout

loadoutDD

Tout

loadoutavg

T

avg

out

⋅⋅=

=

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ −⋅⋅+⎟

⎟⎠

⎞⎜⎜⎝

⎛−=

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛−+⎟

⎠⎞

⎜⎝⎛−=

⋅=

∫∫

∫

2

2

2

22

0

2

2

2

0

0

1

21

21

1

)()(1

33

Power meter simulation• Power meter

– Estimating the average power dissipation of an arbitrary device or circuit driven by a periodic input, with transient circuit simulation

– Consisting• A linear-controlled current source• A capacitor• A resistor

–

– The right-hand side of (6.75) corresponds to the average power drawn from the power supply source over one period

– The value of the node voltage Vy at t=T gives the average power dissipation

( ) ( )

( ) ( )

( ) ( )∫

∫

∫

⋅==

≈>>

⎟⎟⎠

⎞⎜⎜⎝

⎛ −−=

=

−=

T

DDDDyy

DD

T

DDy

yyy

DD

t

yyyy

yy

y

ys

yy

diT

VTVTC

V

diC

TVTCR

diCR

tC

tV

V)(VV

RV

idt

dVC

0

0

0

1 then If

, Assuming

exp

00 asaet is voltagenode theofcondition initial The

ττβ

ττβ

τττβ

β

34

Example 6

35

Power-delay product• For measuring the quality and the performance of a CMOS process

and gate design• The average energy required for a gate to switch its output voltage

from low to high and from high to low• PDP=CloadV2

DD (6.76)– Dissipated as heat during switching– To keep Cload and VDD as low as possible

• PDP=2P*avgτp (6.77)– P*avg is the average switching power dissipation at maximum operating

frequency– Τp is the average propagation delay– The factor of 2, accounting two transitions of the output, from low to high

and from high to low– This result may misleading interpretation that the amount of energy

required per switching event is a function of the operating frequency( )

2

2

max2

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36

Super buffer design (1)• Super buffer

– A chain of inverters designed to drive a large capacitive load with minimal signal propagation delay time

• A major objective of super buffer design– Given the load capacitance faced by a logic gate, design a scaled chain of N

inverters such that the delay time between the logic gate and the load capacitance node is minimized

– The design task is to determine • The number of stages, N• The optimal scale factor, α

37

Super buffer design (2)• For the super buffer

– Cg: the input capacitance of the first stage inverter– Cd: the chain capacitance of the first stage inverter– The inverters in the chain are scaled up by a factor of α per stage– Cload= αN+1Cg– All inverters have identical delay of τ0(Cd+ αCg)/(Cd+Cg)

• τ0: the per gate delay in the ring oscillator circuit with load capacitance (Cd+Cg)

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