Changhwan Shin Department of Electrical Engineering and Computer Sciences

Suppression of Random Dopant-Induced Threshold Voltage

Fluctuations in Sub-0.1μm MOSFET’s with Epitaxial and δ-Doped ChannelsA. Asenov and S. Saini, IEEE Trans. on Electron Devices, Aug 1999

Suppression of Random Dopant-Induced Threshold Voltage

Fluctuations in Sub-0.1μm MOSFET’s with Epitaxial and δ-Doped ChannelsA. Asenov and S. Saini, IEEE Trans. on Electron Devices, Aug 1999

Changhwan Shin

Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720

March 2, 2009

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OutlineOutline

Introduction

» Bulk MOSFET and its scaling challenges

» Random Dopant Fluctuations (RDFs)

MOSFET design to suppress the RDFs

» Adjusting the channel doping profile

Summary

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OutlineOutline

Introduction





Summary

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Incommensurate gains in ION with scaling

» limited carrier mobilitiesstrain Si to enhance eff

» parasitic resistanceuse metallic (silicide) source/drain extensions

Bulk-Si MOSFET Scaling ChallengesBulk-Si MOSFET Scaling Challenges

Substrate

Gate

Source DrainLeff

Nsub

XJ

Lg

Tox

Performance variation

Leakage

» drain currentreduce Tox,eq and Xj

» gate currentuse high- gate dielectric

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Sources of VariabilitySources of Variability

Sub-wavelength lithography:

» Resolution enhancement techniques are costly and increase process sensitivity

Statistical dopant fluctuations» Atomistic effects become significant in nanoscale FETs

Design

Mask

Wafer

250nm250nm 180nm180nm

OPCOPC

90nm and Below90nm and Below

PSM

0°

180°

PSMPSM

0°

180°

0°

180°

OPC0°

180°OPCOPCOPC

0°

180°

A. Asenov, Symp. VLSI Tech. Dig., p. 86, 2007

SiO2Gate

A. Brown et al., IEEE Trans. Nanotechnology, p. 195, 2002

Source Drain

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OutlineOutline

Introduction





Summary

Random Dopant Fluctuations (RDFs)Random Dopant Fluctuations (RDFs)

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“Intrinsic” variation in MOSFET parameters

» Arising from the small number of discrete dopants and their random position in the channel depletion regions

SiO2Gate

A. Brown et al., IEEE Trans. Nanotechnology, p. 195, 2002

Source Drain

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OutlineOutline

Introduction





Summary

MOSFET designs to suppress RDFsMOSFET designs to suppress RDFs

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Fluctuation-resistant architectures via appropriate tailoring of the channel doping profile

» Thin, low doped layer in the channel

Radical solutions» Un-doped channel MOSFET (UTB, FinFET, DG, gate-all-

around)» More demanding of technological modification

Conventional Epitaxial Epitaxial w/ δ-doping

3D atomistic simulation results3D atomistic simulation results

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Epitaxial MOSFET

» σVt is evaluated via 3D atomistic simulator Results

» σVt dramatically reduced for the first 10nm of epilayer

» Maximum depi should be considered with Tox, Xj, Leff

» Leff/depi > 5

» Boron diffusion into epi-layer; tolerable up to 1017cm-3

» Dependence of σVt on the back-doping; Screening effect The holes in the heavily

doped region screen the charge of the discrete random acceptors in the thin depletion layer

3D atomistic simulation results3D atomistic simulation results

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Epitaxial MOSFET with the delta doping

Results» If the δ-doping is only partially depleted (i.e. depi is deep

enough, or screen effect is valid), the doping concentration NA

b increase will result in σVt reduction.

» Additional degree of freedom in tailoring the threshold voltage

Conventional Epitaxial Epitaxial w/ δ-doping

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OutlineOutline

Introduction





Summary

SummarySummary

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Fundamental issue; RDFs in deep sub-micron MOSFET

3D statistical atomistic simulations to study RDFs

Random dopant-induced threshold voltage fluctuations can be significantly suppressed in MOSFET’s with low-doped epitaxial channels.

Q & AQ & A

Thank you for your attention!!!

Questions?

Changhwan Shin Department of Electrical Engineering and Computer Sciences

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