Ch27 Phase-locked Loops 1290

Phase-Locked Loops

Jieh-Tsorng Wu

July 16, 2002

A

1896

E S National Chiao-Tung UniversityDepartment of Electronics Engineering

Phase-Locked Loops (PLLs)

A Vi c

oAFilter

PhaseDetector

LoopVFO

Ai = g1 (ωit + θi) Ao = g2 (ωot + θo) ωo = ωoo + Kc · Vc

• g1 and g2 are periodic functions with 2π period.

• When the loop is locked, the frequency of the VCO is exactly equal to the averagefrequency of the input.

• The loop filter is a low-pass filter that suppresses high-frequency signal componentsin the phase difference.

PLLs 27-2 Analog ICs; Jieh-Tsorng Wu

Phase-Locked Loops (PLLs)

Applications:

• Automatic frequency control.

• Frequency and phase demodulation.

• Data and clock recovery.

• Frequency synthesis.

References:

• Roland E. Best, “Phase-Locked Loops,”, 2nd Edition, McGraw-Hill, Inc., 1993.

• Dan H. Wolaver, “Phase-Locked Loop Circuit Design,” Prentice-Hall, Inc., 1991.

• Floyd M. Gardner, “Phaselock Techniques,” 2nd Edition, John Wiley & Sons, 1979.


Basic Model

Vd VcPD

DetectorPhase VFO

F(s)

Filter

θi θo

Vd = Kd (θi − θo) ωo = ωoo + Ko × Vc

Ko/s

When the PLL is locked,

Vd (s) = Kd · [θi(s) − θo(s)] = Kdθe(s) θe = θi − θo

Vc(s) = F (s) · Vd (s)∫ωodt = ωoot +

∫KoVcdt = ωoot + θo ⇒ θo(s) = Vc(s) ·

Ko

s

• θe is the phase error, Kd is the phase-detector gain factor, and Ko is the VCO gainfactor.


Basic Model

System equations are

Vd = Kd · (θi − θo) = Kd · θe Vc = F (s) · Vd θo = Vc ·Ko

s

The transfer functions are

θo

θi

=KoKdF (s)

s + KoKdF (s)= H(s)

θe

θi

=s

s + KoKdF (s)= 1 − H(s)

Vc

θi

=sKdF (s)

s + KoKdF (s)=

s

Ko

· H(s)

⇒ H(s) =∆ωo

∆ωi

= Ko ·Vc

∆ωi

∆ωi = ωi −ωoo ∆ωo = ωo −ωoo

• H(s) is the closed-loop transfer function.


Second-Order PLL — Active Lag-Lead Filter

Vi Vo

R2

1R

C

F (s) = −sτ2 + 1

sτ1

τ1 = R1C

τ2 = R2C

H(s) =2ζωns +ω

2n

s2 + 2ζωns +ω2n

ωn =

√KoKd

τ1ζ =

ωn

2· τ2

• ωn is the pole frequency of the loop.

• ζ is the damping factor. Qp = 1/(2ζ ) is the pole quality factor.


Second-Order PLL — Passive Lag-Lead Filter

Vi Vo1R

R2

C

F (s) =sτ2 + 1

sτ1 + 1

τ1 = (R1 + R2)C

τ2 = R2C

H(s) =s[2ζωn −ω

2n/(KoKd )

]+ω

2n

s2 + 2ζωns +ω2n

ωn =

√KoKd

τ1ζ =

ωn

2

(τ2 +

1KoKd

)

• If R2 = 0, then

τ1 =1

R1C=

1ωLF

ωn =√KoKdωLF ζ =

ωn

2KoKd

H(s) =ω

2n

s2 + 2ζωns +ω2n


High-Gain Second-Order PLL Frequency Response

If KoKdτ2� 1 in the passive filter, then

Hpassive(s) ≈ Hactive(s) =2ζωns +ω

2n

s2 + 2ζωns +ω2n

And the −3 dB bandwidth of H(s) is

ω−3dB = ωn

[2ζ2 + 1 +

√(2ζ2 + 1)2 + 1

]1/2

• Usually choose ωn < ωi/10 to remove the high-frequency components at ωi , 2ωi ,. . . , existing in the phase detector’s output.

• The PD output’s high-frequency components can show up as spurious tones in thefrequency spectrum of the PLL’s output.


High-Gain Second-Order PLL Frequency Response

ω| H

( j

) |

(d

B)

0.1 1 10

10

5

0

-5

-10

-15

-20

Frequency (ω/ωn)

ζ = 5.0

ζ = 2.0

ζ = 0.707

ζ = 0.5

ζ = 0.3


Step Response of a Two-Pole System

Consider the following two-pole transfer function

H(s) =ω

2n

s2 + 2ζωns +ω2n

Poles = s1,2 =(−ζ ±

√ζ2 − 1

)ωn

• If ζ > 1, the system is overdamped, and both poles are real.

Step Response = 1 − 1

2√ζ2 − 1

(1k1

e−k1ωnt − 1k2

e−k2ωnt

)

k1 = ζ −√ζ2 − 1 k2 = ζ +

√ζ2 − 1

• If ζ = 1, the system is critically damped, and both poles are at −ωn.

Step Response = 1 − (1 +ωnt)e−ωnt ≈ 1 − e−ωnt/(2ζ ) if 4ζ2� 1


Step Response of a Two-Pole System

• If ζ < 1, the system is underdamped.

Step Response = 1 −(ζωn

ωd

· sinωdt + cosωdt

)e−ζωnt ωd =

√1 − ζ2 ·ωn

% Overshoot = 100e−π/√

1/ζ2−1

1

Overshoot

Error Band

t

Ste

p R

esp

on

se

• For PLL, choose ζ > 1/√

2 = 0.707 to avoid excessive ringing.


Phase Jitter

ProbabilityDensity

Vs nc

nt

VN

θn θn

pdf = 1√2πσn

e−θ2

n/(2σ2n)

v(t) = s(t) + n(t) = Vs sin(2πfot) + n(t)

n(t) = nc(t) sin(2πfot) + nt(t) cos(2πfot)

The phase jitter is

θn(t) = tan[

nt(t)

Vs + nc(t)

]≈

nt(t)

Vs


Phase Jitter

Assume that

n2 =12· n2

c +12· n2

tn2c = n2

t

Then, we have

σ2n = θ2

n =n2t

V 2s

=n2

V 2s

=12· 1SNR

• SNR is the signal-to-noise ratio, and can be expressed as

SNR ≡V

2s /2

n2


Phase Noise

PowerSpectralDensity

Freq

Ps

Pssb

L(fm)

fo

fm

v(t) = Vs sin [2πfot + θn(t)]


Phase Noise

• The phase noise L(fm), usually in dBc, is the ratio of the single-sideband (SSB) powerin a 1-Hz bandwidth fm Hz away from the carrier to the total signal power, i.e.,

L(fm) ≡Ps

Pssb

• Let Sθn(f ) be the power spectral density of θn(t) in frequency domain, it can be shown

that

Sθn(fm) ≈ 2L(fm) and θ2

n =∫ ∞0

Sθn(f )df


PLL Noise Response

F(s)θi θo

θn,i θn,vf onvc

Kd Ko/s

Let θn,o be the phase noise in θo, we have

Sθn,o

Sθn,i

=

∣∣∣∣ KoKdF (s)

s + KoKdF (s)

∣∣∣∣2

s=jω

= |H(jω)|2

Sθn,o

Sθn,vf o

=

∣∣∣∣ s

s + KoKdF (s)

∣∣∣∣2

s=jω

= |1 − H(jω)|2

Sθn,o

Snvc

=

∣∣∣∣ Ko

s + KoKdF (s)

∣∣∣∣2

s=jω

=

∣∣∣∣[1 − H(jω)] ·Ko

jω

∣∣∣∣2


PLL Noise Response

Consider only a white noise Sθn,i(f ) in θi ,

θ2n,o =

∫ ∞0

Sθn,i(f )|H(j2πf )|2df = Sθn,i

(f ) × BL

BL is the noise bandwidth of H(j2πf ), i.e.,

BL ≡∫ ∞0|H(j2πf )|2df

For the 2nd-order PLL with active lag-lead filter

BL =12ωn

(ζ +

14ζ

)

• BL,min occurs at ζ = 0.5.

• BL < 1.25BL,min for 0.25 < ζ < 1.0.


Phase Detection Using Analog Multiplier

V1

V2

Vd

Vd

θe

12π

π

32π 2π

−12π

-π

−32π

−2π

V1(t) = V1 sin(ωt + θ1) V2(t) = V2 cos(ωt + θ2)

Vd (t) = kV1(t)V2(t) =12kV1V2 [sin(θ1 − θ2) + sin(2ω + θ1 + θ2)]


Phase Detection Using Analog Multiplier

The 2ω component will be filtered out by the loop filter, hence consider the dc componentonly

Vd =12kV1V2 sin(θ1 − θ2) = Kd · sin(θe) θe = θ1 − θ2

• Kd is the phase-detector gain factor, and θe is the phase error.

• If θe� 1, vd ≈ Kdθe.

• V1(t) and V2(t) are 90◦ out of phase when θe = 0.


PLL Tracking Performance — Hold-In Range

From the final value theorem

limt→∞

θe(t) = lims→0

sθe(s) = lims→0

s2θi(s)

s + KoKdF (s)

The hold-in range, ∆ωH , is the frequency range in which a PLL can maintain lockstatically.

ωi = ωo + ∆ωH θi(t) = ∆ωH · t θi(s) = ∆ωH/s2 ⇒ lim

t→∞θe(t) =

∆ωH

KoKdF (0)

• For a sinusoidal PD, the criterion becomes

limt→∞

sinθe(t) =∆ωH

KoKdF (0)< 1 ⇒ ∆ωH = KoKdF (0)

For a 2nd-order PLL with active filter, F (0)→∞, thus ∆ωH →∞.


PLL Tracking Performance — Pull-Out Range

The pull-out range ∆ωPO is the frequency-step limit below which the PLL does not skipcycles but remains in lock.

• For a sinusoidal PD

∆ωPO = 1.8ωn(ζ + 1) for 0.5 < ζ < 1.4


Noisy PLL Tracking Performance

Define the SNR of a PLL as

SNRL ≡1

2θ2n,o

• As a rule of thumb, SNRL > 6 dB is required for stable operation.

For low SNRL, the VFO phase occasionally slips one or more cycles as compared to theinput. Define TAV as the average time between cycle slips.

• For a 1st-order loop TAV ≈ π4BL

e4SNRL, where BL is the PLL noise bandwidth.

• For a 2nd-order loop with ζ = 0.707 TAV ≈ 1BLeπSNRL.

• The slips of a 1st-order loop are almost always single, isolated events.

• The slips in a 2nd-order loop tend to bunch in bursts.


PLL Acquisition Behavior

i VoV F(s)Phase

Detector

VFOLoop Filter

• The process of bringing a PLL into lock is called acquisition.

• Acquisition is inherently a nonlinear phenomenon.

• An nth-order PLL contains n integrators (VFO, capacitors, . . . ). With each integratorthere is associated a state variable of the loop: phase, frequency, frequency rate,and so on. To force the loop into lock, it is necessary to bring each of the statevariables close to the corresponding parameters of the input signal. Therefore, weshould speak of phase acquisition, frequency acquisition, and so forth.


Phase Acquisition of a First-Order Loop

ViVd

VoPhase

Detector

VCO

θe

θ̇eKoKd

∆ωKoKd− sinθe

Vd = Kd · sinθe ωo = ωoo + Ko · Vd θe = θi − θo

θe = θi − θo = ωit −ωoot −∫ t

0KoKd sinθedt − θo(0)

⇒dθe

dt= θ̇e = ∆ω − KoKd sinθe ∆ω = ωi −ωoo

• The loop is locked when θ̇e = 0.

• There is no cycle skipping in the acquisition process.


Phase Acquisition of a Second-Order Loop

The lock-in range, ∆ωL, is the frequency range over which the PLL can acquire lockwithout cycle slipping.

By practical considerations, the lock-in process of a higher-order loop isso fast that it can be approximated bythe phase acquisition process of a 1st-order loop with gain K = KoKdF (∞).

log f

log |F (j f )|

F (∞) = τ2τ1

• For a PLL with with sinusoidal PD,

Lock-In Range = ∆ωL ≈ KoKdF (∞) = 2ζωn Lock-In Time = TL ≈1ωn


Frequency Acquisition — The Pull-In Process

The pull-in range, ∆ωP , is themaximum initial frequencyoffset for the pull-in processto occur.

t

∆ω

ωi

ωo

Tp

• For a 2nd-order PLL,

Pull-In Range = ∆ωP ≈8π

√ζωnKoKd −ω2

n ≈8π

√ζωnKoKd if KoKd � ωn

Pull-In Time = Tp ≈∆ω

2

2ζω3n


Aided Frequency Acquisition — Frequency Sweeping

Vi LoopFilter

PhaseDetector

DetectorLock Sweep

Generator

VFO

• Use sweep to bring the VFO close to the frequency of locking.


Aided Frequency Acquisition — Loop Filter Switching

Vi PhaseDetector

DetectorLock

VFO

Low R if unlocked; High R if locked

Loop Filter

Low R

High R

• The frequency pull-in can be painfully slow in a narrowband loop. Sometimes, a widerloop bandwidth is preferred.


Aided Frequency Acquisition — Dual Loops

iV LP

LP

Detector Filter 1

Filter 2

Phase

VFO

DetectorFrequency

• Contains a phase-locked loop (PLL) and a frequency-locked loop (FLL).

• The FLL should dominate during frequency acquisition.

• The PLL should dominant when the phase is locked.


Digital Phase-Locked Loops (DPLLs)

oVViVd VcF(s)

1/N

PD

Loop Filter

VFO

Frequency Divider

To calculate loop dynamics, combine the VFO and the frequency divider as a new VFO.

ωo = ωoo + Ko · Vd ⇒ ω′o =ω

N=

ωoo

N+Ko

N· Vd = ω′oo + K ′o · Vd

ω′oo =ωoo

NK ′o =

Ko

Nθ′o =

θo

N

• θi and θo are not available except during the rising and falling transitions.


XOR Phase Detector

u1

u2

Q

u1

u2Q

0

u1

u2

Q

u1

u2

Q

Averaged Q

θeπ2

π−π2

−π

• The PD characteristic is strongly dependent on the duty-cycle of u1 and u2.


Edge-Triggered Set-Reset Phase Detector

S

RQ

u1

u2

Q

u1

u2

Q

u2

u1u1

u2

Q

Frequency Discrimination Capability

0

Averaged Q

u1

u2

Q

u1

u2

Q

θeπ 2π−π−2π


Edge-Triggered Set-Reset Phase Detector

• The PD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.

• If f1 � f2 or f1 � f2, the PD has frequency discrimination capability, which canimprove frequency acquisition speed of the PLL.

• However, when f1 ≈ f2, the frequency-sensitive behavior is lost, and the PLL relys onthe pull-in process for frequency acquisition.


Sequential Phase-Frequency Detector (PFD)

RQD

u1

u2

UP

0

u1

u2

UP

Averaged (UP-DW)

RD Q

1

1

u1

u2

UP

DNDN

DN

θe

π 2π−π−2π


Sequential Phase-Frequency Detector (PFD)

• The PFD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.

• The PFD can discriminate the frequency difference for even the smallest f1 − f2.

• A PLL with the PFD can have infinite pull-in range. The frequency acquisition aidprovided by the PFD is akin to frequency sweeping.

• When using the PFD, a missing transition or an extra one in either u1 or u2 can causea large error signal to appear. The effects will propagate for more than one cycle.Great caution is required to use the PFD in a noisy environment.


Charge-Pump Phase-Locked Loops

ViVo

Vc

IP

IP

IeUP

PFD

R

C

VFO

DN

u1

u2

The “on” time of either UP or DN is tp = |θe|/ωi for each period 1/fi of the input signal.The average error current Ie over a cycle is

Ie = IP ×tp

Ti= IP ×

θe

2πωi = 2πfi =

2πTi



The voltage Vc can be expressed as

Vc(s) = Ie(s)(R +

1sC

)= θe(s) ×

IP

2π

(R +

1sC

)Vc(s)

θe(s)= KdF (s) =

IP

2π

(R +

1sC

)

The VFO has the following characteristic:

ωo = ωoo + Ko · Vc ⇔ fo = foo + K ′o · Vc K ′o =Ko

2π

Using the continuous-time approximation, we have

θe(s)

θi(s)= He(s) =

s2

s2 + 2ζωns +ω2n

θo(s)

θi(s)= H(s) = 1 − He(s)

ωn =(K ′o ×

IP

C

)1/2

ζ =12

[K ′o × (IP R) × (RC)

]1/2



• The PLL behaves as a 2nd-order loop with active lag-lead filter.

• Discrete-time model can be used for more accurate analysis. Reference: Hein, z-Domain Model for Discrete-Time PLLs, Trans. CAS, 11/88, pp. 1393–1400.

• During the pump interval tp, a voltage step of IP R occurs at the VFO input. Thisgranularity effect may be intolerable in some systems.

• The voltage step IP R may overload the VFO, making the previous linear analysisinvalid.

• The granularity effect can be mitigated with an additional capacitor Cp in parallel withthe earlier RC network, thus forming a 3rd-order PLL.

• Reference: Floyd Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Commun.,Nov. 1980, pp. 1849–1858.


PFD and Charge-Pump Filter

IP2

IP1

Dead ZoneDN

UPS1

S2 C

RQD

RD Q

1

1

u2

u1

Vc

∆Vc

θe

• The dead zone is caused by the slowness of the S1 and S2 switches.


PFD and Charge-Pump Filter

• When θe falls in the dead zone, the PFD’s conversion gain is decreased, causing areduction in ωn and ζ , and the degradation of θo phase noise.

• The dead zone can be eliminated by allowing UP and DN to be activatedsimultaneously for a short time even if the phase difference is zero. Then, anymismatch between IP 1 and IP 2 can cause a phase offset and consequently spursin the output spectrum.

• The finite output impedance of the IP 1 and IP 2 current sources can also cause phaseoffset.

• Charge sharing in the S1 and S2 switches can also cause glitches at Vc.


PFD with Delayed Reset

DN

UP

u2

u1

Delay


Third-Order Charge-Pump PLLs

IP

IP

Ie VcUP

DN 0R1

C1C2

ωωz

ωtωp

|L(jω)| (dB)

The loop filter transfer function is

Vc(s)

θe(s)= KdF (s) =

IP

2π

[(R1 +

1sC1

)‖ 1sC2

]=

IP

2πs(C1 + C2)×

sR1C1 + 1

sR1(C1‖C2) + 1

ωz =1

R1C1ωp =

1

R1(C1‖C2)


Third-Order Charge-Pump PLLs

The loop gain of the 3-order PLL is

L(s) =Ko

s× KdF (s) =

K′oIP

s2(C1 + C2)×

s/ωz + 1

s/ωp + 1

Let ωt/ωz = α > 1 and ωp/ωt = β > 1, then

ωt ≈K′oIP

(C1 + C2)ωz

= K ′o · IP R1 ·C1

C1 + C2

R1 =1

K ′oIP·ωt C1 = K ′oIP ·

α

ω2t

C2 = K ′oIP ·1

β ·ω2t

• α = 4 and β = 4 gives a phase margin ≈ 60◦.


Multi-Path Charge-Pump Filter

V aV b

V c

Ca

Rb Cb

V c

V a

V b

Ie1

Ie2

ωωz ωt ωp

Ie1 = IP 1 ×θe

2πIe1 = IP 2 ×

θe

2π


Multi-Path Charge-Pump Filter

The loop filter transfer function is

Vc(s)

θe(s)= KdF (s) =

IP 1

2π· 1Ca

+IP 2

2π

(Rb‖

1sCb

)=

IP 1

2πsCa

×sRb

(Cb + Ca ·

IP 2IP 1

)+ 1

sRbCb + 1

1ωz

= Rb

(Cb + Ca ·

IP 2

IP 1

)≈ RbCa ·

IP 2

IP 1

1ωp

= RbCb

The loop’s unity-gain frequency is

ωt ≈K′oIP 1

Caωz

= K ′o · IP 2Rb

• ωz, ωp, and ωt, can be set using smaller capacitors and resistors.

• Reference: J. Craninckx and M. Steyaert, A Fully Integrated CMOS DCS-1800Frequency Synthesizer, JSSC, 12/98, pp. 2054–2065.


Ch27 Phase-locked Loops 1290

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