Beta Multiplier based current reference

19
EEE523: ADVANCED ANALOG IC DESIGN PROJECT 1 CMOS -MULTIPLIER BASED CONSTANT-GM CURRENT REFERENCE Current Mirrors NAME (LAST, FIRST, MI) : PARAMAIAHGARI SRIKANTH R ASU ID # : 1206321047

description

Beta Multiplier based current reference

Transcript of Beta Multiplier based current reference

  • EEE523: ADVANCED ANALOG IC DESIGN

    PROJECT 1

    CMOS -MULTIPLIER BASED

    CONSTANT-GM CURRENT REFERENCE

    Current Mirrors

    NAME (LAST, FIRST, MI) : PARAMAIAHGARI SRIKANTH R

    ASU ID # : 1206321047

  • Objective:

    1 Objective In this project, we will design three -multiplier based current reference circuits, using CMOS transistors in TSMC 0.25 CMOS design library. For the current setting resistor R, we can use an ideal zero-temperature coefficient resistor from analogLib library. The resistor R and multiplication value K sets the branch currents. We will size the transistors, K and R to optimize in such a way that the reference currents Iref1 , Iref2 match for a wide range of supply voltage Vdd for designs 1, 2 and 3 and try to be as constant as possible. Also, We would use this current to bias an NMOS transistor and prove that its gm is constant, just like the current setting resistor R across process, voltage and temperature. Design Procedure: First of all to make sure the startup circuit work properly, we need to make sure the VGS of startup transistor less than Vth after the circuit turns on completely. To make sure VGS of stratup transistor is less than Vth , we need to increase the length of the diode connected PMOS or NMOS. For all three designs, considering M1 and M2 NMOS transistors applying KVL around the

    loop, we can write

    Vgs1=Vgs2+I2R.

    which can only be valid if VGSI > VGS2. To ensure that this is the case, we use a larger value of

    in M2, that is, we multiply-up M1's in M2 so that less gate-source voltage is needed to

    conduct Iref. This is done by simply using a larger width in M2.The resulting circuit is called a

    Beta-multiplier reference circuit.

    =(2/((/)))+

    Assume 2=(/)2 = K 1 Therefore, W2 = KW1

    Solving for I2 from the above two relations, we get

    2=(2/(2(/)))1(11/)2

    Using the above equation wr can solve for R for given reference current Iref=10uA.

    Note that we have no dependency on VDD. For k=4, solving for Iref, we have a constant gm

    biasing circuit.

    Gm= Sqrt(2*k*w/L*Iref)= 1/R.

    In this pro ject, k is chosen to be 4 in three designs.

    To find the correct R value at Iref=10A, parametric analysis in Cadence is performed by

    varying the R(Because the calculated value of R is not exact due to ignoring body effect and

    channel length modulation effects).

  • All the transistors are sized by assuming Vdsat=125 mV.

    For design3, to achieve zero temperature coefficient for Vref, we need to find the

    correct value of resistor temperature coefficient to compensate it.

    The procedure to find the temperature coefficient is as follows :

    Plot dVth/dT of NMOS vs temperature (The Vth can be obtained from Calculator-->info-->op-->

    select the NMOS device and select Vth). Find the value of dVth/dT at 27C from the plot.

    Plot (1/Kp)*(dKp/dT) of the NMOS device vs temperature (The betaeff parameter from the op

    of NMOS should be divided by its (W/L) to get Kp). Find the value of (1/Kp)*(dKp/dT) at 27 C

    from the plot.Now use the equation (1/R)*(dR/dT) = R*Kp*(dVth/dT) (1/Kp)*(dKp/dT) and

    find out (1/R)*(dR/dT) using the values calculated above. This value corresponds to the

    Temperature coefficient1 parameter in the resistor model used in cadence. Now we can

    sweep the temperature coefficient value of the resistor and select the value of temperature

    coefficient 1 such that dVref/dT is minimum at 27C.

  • Design1:

    Schematic:

    Sizing and biasing:

    Parameter Min Nom Max

    VDD 2.0V 2.5V 3.0V

    Iref1 9.043u 9.997uA 10.91u

    Iref2 9.042u 9.997uA 10.91u

    gm 110.6u 113.8u 117u

  • These are obtained from Iref vs Vdd plots attached below.

    And it can be observed from the below schematic that Iref1=Iref2=10uA for 2.5V.

    R= 7.757 kOhms.

    Device W(um) L(um) Vgs-Vt(m

    V)

    Vds(mV) Ibias(uA)

    M1 2.775 0.6 136.9 594.6 10

    M2 11.1 0.6 81.96 796.9 10

    M3T 11.925 0.825 146 -737.4 10

    M3B 7.95 0.9 151.2 -1.168 10

    M4T 11.925 0.9 146 -736 10

    M4B 7.95 0.6 151.3 888.5 10

    MS1 0.45 45 1.554V -2.445V 0.6

    MS2 0.45 0.3 44.7m 1.169V 10.01f

    MS3 0.45 0.6 132m 45.2 0.6

  • Iref1,Iref2 Vs Vdd: It can be observed from the below plot that Iref1 and Iref2 are with +/- 5% (
  • Vref vs Temperature:

    Gm vs Temperature: Theoritical gm=1/R= 1/7.754K = 128.9 uA/V. which is

    close to practical gm=129uA.

  • Design2:

    Schematic: Current of 10 uA is flowing through both the legs as observed

    at the resistor.

  • Sizing and Biasing:

    Design questions: R=7.341 kOhms(parametric analysis)

    Parameter Min Nom Max

    VDD 2.0V 2.5V 3.0V

    Iref1 9.54uA 10uA 10.2u

    Iref2 9.51uA 10uA 10.25u

    Gm 128uA/V 130uA/V 131uA/V

  • DESIGN QUESTIONS:

    Device W L VGS-Vt VDS Ibias

    M1 2.775um .6um 136mV 594.6mV 10uA

    M2 11.1um .6um 82.2mV 796.9mV 10uA

    M3T 11.925um .9um 141mV 737mV 10uA

    M3B 7.95um .9um 151.4mV 1.168V 10uA

    M4B 7.95um .9um 151.2mV 889.5V 10uA

    M4T 11.925um .6um 140.6mV 736mV 10uA

    M1T 7.95um .6um 141.8mV 479.9mV 10uA

    M2T 7.95um .6um 144mV 859.5mV 10uA

    Startup_n 0.45um 0.6um 131mV 45.2mV 0.697uA

    Startup_p 0.450um 45um 1.553V 2.455V 0.697uA

    NMOS_switch 0.450um .6um 45mV 1.169V 10fA

    Iref1,Iref2 Vs Vdd: It can be observed from the below plot that Iref1 and Iref2 are with +/- 5% (

  • Vref vs Vdd:

    Vref vs Temperature:

  • Gm vs Temperature: Theoritical gm=1/7.341K= 136 uA/V close to practical.

  • Design3:

    Schematic:

  • Sizing and biasing:

  • Design questions: R=7.4265 kOhms(parametric analysis)

    Parameter Min Nom Max

    VDD 2.0V 2.5V 3.0V

    Iref1 9.9996uA 10uA 10.0006u

    Iref2 9.99975uA 10uA 10.00095u

    Gm(zero temp co R) 127.7uA/V 129.1uA/V 130.2uA/V

    DESIGN QUESTIONS:

    Device W L VGS-Vt VDS Ibias

    M1 2.775 .6um 136mV 594mV 10uA

    M2 11.1um .6um 82.2mV 520mV 10uA

    M3 11.925um .9um 141mV 1.905mV 10uA

    M4 11.925um .9um 140.6mV 1.905mV 10uA

    MA1 2.775um .6um 135mV 1.744mV 12.27uA

    MA2 2.775um .6um 145 1.77 12.25uA

    MA3 11.925um .9um 122mV 755mV 12.27uA

    MA4 11.925um .9um 122mV 730mV 12.25uA

    Startup_n 0.45um 0.6um 131mV 45.2mV 0.697uA

    Startup_p 0.450um 45um 1.553V 2.455V 0.697uA

    NMOS_switch 0.450um .6um 45mV 1.169V 10fA

  • Iref1,Iref2 Vs Vdd: For entire range of Vdd Matching error between Iref1

    and I ref2 is < 5%. It is very small as observed from below plot.

    Vref vs Vdd:

  • Vth Vs Temperature:

    Kpn vs Temperature:

  • Vref vs Temperature:

    With Zero temperature coefficient resistor

    With 5m temp coefficient resistor

  • Gm vs Temperature

    Zero temperature coefficient resistor

    With 5m temperature coefficient resistor: