Beam diagnostics developments at LAPP:

Digital part

CTF3 Collaboration Meeting 16-01-2007

Louis Bellier, Richard Hermel, Yannis Karyotakis,

Jean Tassan, Sébastien Vilalte

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Front-end

• Design divided in 3 parts:» Analog front-end board (4 inputs → 1 Σ and 2Δ)» Digital front-end board (sampling)» PCI acquisition board (far from radiation)

4

Δ1

Σ

Δ2

ADC boardAnalogpart Acquisition

Near the beam <10m

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Digital front-end

Sampling Solution:

Using the SAM analog memory.

- Developed by the CEA for HESS2.- 2 memories (2x256 points) per channel

~ we need at least 300pts during 1,5 µsor 140 ns after CR (1 memory)

- Sampling 200MSps or more.-Better delay line stability over 300MHz

- Rad-Hard 200kRad → After the SAM: ADC rad-Hard, 14 bits, 800kSps.

↳Synchronization with the SAM output

→ 35kRad technology due to FPGA

CEA SAM Memory

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Digital front-end principle

FPGA

14

14

14

Σ

∆1

∆2

SAM ADC

SAM

SAM

clk1

clk1

clk1

clk

clk1

clk1

clk1

clk1

clk = 200MHz clk1 = 800kHz

ADC

ADC

SPECS Mezzanine board

// BusRJ 45

clk

clk

clk

BlockingCTF3 clock

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Digital front-end board

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Acquisition

100m

Master Board

100m

Master board4 channels

Service boxService box

Specs slave

Digital front-endboard

Digital front-endboard

Digital front-endboard

Specs slave

Specs slave

Ethernet cable

The chained specs mezzanines ( ~4 at least)

Control room

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Specs PCI Board

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Sampling cycle

10 waiting for blocking signal

20 write in analog memory

40 sampling with ADC

blocking pulse

cell written 3x256

30 read analog memory

data sampled

data stored x3x256

41 write in FPGA ’s ram

50 send interruption to specs

wait for read from specs

60 send the data

data sent x3x256

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Beam diagnostic

Signals(Σ,Δ1,Δ2)

DigitalFront-end

13Trigger

SPECSBus

1

1..4

SPECSMaster

41Gateway(Linux)

21

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Disposition around the beam

Digital Front-endboards in crate

Ethernet cable to the acquisition

~5 metersAnalog signals by RJ45 (SFTP cat.6)

Analog front-endunder the beam

Power supply and controldistribution board for analog part

Blocking and CTF3 clock

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Dosimeters

BPI06088Gy

BPI06227Gy

7Gy

BPI064545Gy

7Gy

BPI066515Gy

BPI06929Gy

BPI07226Gy BPI0758

11GyBPI013058Gy

Integrated dose in Grayduring the last run (3weeks)

Girder

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Evolution since the last meeting

Tests and debug of the digital front-end prototypeData transmission with the SPECS chainAnalog board configuration through SPECS and digital

partAnalog memory of 512 or 1024 disable =>2

memories of 256 points on next prototypeSoftware development (link with FESA)Sum channel “positive and negative”Dosimeters around the TL1 during last

commissioning1 prototype still in production

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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Conclusion

Testing one prototype during the next run. If digital part only after CR, just one analog memory

necessary by channel. (pulse of 140ns)First Δ in front-end and final differences (ΔV and

ΔH) in software after transmission.Software development with FESA.Possibility to install Lapp solution on CR after

conclusive results on TL2. Installation on other part of the accelerator?

16/01/2007 CTF3 Collaboration Meeting Louis Bellier

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