11

Basic Input and Output MethodsPolling I/O

Interrupt I/O

2

• Imagine a μP is executing a number crunching program

• Note: the program is stored in ROM and data is stored in RAM, both chips of which are not shown here.

BasicμP

• Now, consider a peripheral device, such as a keyboard, mouse, or the capacitive touch sensor on a smart phone.

• When you tap on your phone, the capacitive touch sensor hardware outputs the coordinates of where you tapped.

• When a user presses a key, the Keyboard device outputs the ASCII code of the key.

• If the μP is busy running some other program, how does the Keyboard (or Tapping Hardware) get the attention of the μP so that it can pass the ASCII code of the key (coordinates of where you tapped) to the μP?

PCIA1

PCIA2

PCIA3

SCIASCIA

3

BASIC INPUT/OUTPUT (IO) METHODS

• Method 1: Polling– μP program may have a polling routine, which polls the

peripheral devices to determine if they have data available, or generally if they need service.• When a peripheral device needs service, it will cause a bit, in

the status register of its interface adapter, to be set.• The μP does polling by reading a bit in the status register in the

interface adapter for the device.• Polling becomes increasingly inefficient as the number of

devices increases, since many devices don’t need service most of the time.

4

BASIC INPUT/OUTPUT (IO) METHODS

• Method 2: Interrupt Request– The μP does not poll the devices, but it allows the

devices to interrupt its program when the devices need service.

– When service is needed, a peripheral device will interrupt the μP via a voltage signal on a wire, which is connected to the μP• The interrupt request signal on a wire causes the current

program to be temporarily stopped, and causes an Interrupt Service Routine (ISR) to be run.• When there are many devices, it is more efficient than polling

since a μP only responds when a device requires service.

5

SOFTWARE POLLING FLOW CHARTEQUAL PRIORITY

• A polling routine can be implemented as a subroutine and run in a periodic manner:

loop ldaa #$FF//other instructionsjsr polling//other instructionsbra loop

• Note: this does not implement priority since each device is given the opportunity to be serviced in the loop.

KP?

Service KP

LED?

Service LED

SW?

Service SW

N

N

Y

Y

Y

N

Enter PollingSubroutine

RTS

6

PRIORITY POLLING• This design implements priority, since only the highest

priority device is serviced each time the polling routine is run.

• Not all of the devices are given the opportunity to be serviced.

• Priority is established by the order of the devices in the list.

polling brset D1SR, BitToTest, doD1brset D2SR, BitToTest, doD2…brset DnSR, BitToTest, doDnrts

doD1 ; D1 service routinerts ; Return from polling

doD2 ; D2 service routinerts ; Return from polling …

doDn ; Dn service routinerts ; Return from polling

7

Interrupt Processing Overview

8

• Except– A subroutine is called by the JSR instruction

JSR someSub

• While– An Interrupt Service Routine is caused to run by

the assertion of a voltage on a μP pin.

Peripheral Device (D1) IRQn

μPD1_ISR TSX

LDAA 4,x…RTI

Run my routine!

9

INTERRUPT COMPONENTSof a Basic μP

1. Mechanism of initiating an Interrupt Request

2. Interrupt Mask

3. Preserving the Context of the Machine

4. Interrupt Vector

5. Running the Interrupt Service Routine (ISR)

6. Return From Interrupt

10

INITIATING AN INTERRUPT REQUEST

• When a device needs service, it asserts a voltage on a wire which is connected to the μP’s IRQ pin.

• If interrupts are enabled, this ultimately causes the ISR to run.

• Two ways to initiate a request:– Level (usually active low)– Edge (usually negative edge)

Basic μP

11

INTERRUPT MASKEnabling/Disabling Interrupts

• The I-bit in CCR is the Interrupt Mask• If I = 1, processor does not respond to IRQSEI is the “Set Interrupt Mask” instruction.

• If I = 0, processor does respond to IRQCLI is the Clear Interrupt Mask instruction.

I N Z V CCCR

12

• For this basic μP, the registers are automatically preserved when an ISR is called.– Note: preserving registers must be done by the programmer for a subroutine.– In an ISR, all registers, except SP, are preserved, automatically (without programmer involvement).

SP Before interrupt

SP at the Beginning of the ISR

Stacking Context of Machine

13

• The Interrupt Vector is the address of the ISR– Actually the address of the 1st instruction of the ISR– It “points” to the ISR; hence it is called a “vector”

• In this Basic μP, the IRQ vector is stored at: FFF8:FFF9, which is the 1st location of the vector table.

IRQ VectorAddress

14

• Some μPs do not have an interrupt vector– Their ISR starts at a fixed address, like $0004.

• The processor in this course has an interrupt vector– It is set by the designer, i.e., you.– The designer writes the ISR in assembly language,

thus knowing its starting address; and, also in assembly language, arranges that the starting address is written or burnt into ROM locations FFF8:FFF9, through assembler directives.

15

Interrupt Service Routine (ISR)• The ISR runs and services the device that requested service.• The ISR is application specific.• For many devices, the ISR will perform polling to determine

which device requested the service, and run its routine accordingly.

ISRStart //1st instruction of the ISR……

//2nd last instructionRTI

16

(Before RTI)

(After RTI)

The RTI instruction unstacks the context of the machine, thus restoring the state of the μP to that in which it

was prior to being interrupted.

17

INTERRUPT TIMING OVERVIEW

18

INTERRUPT TIMING OVERVIEW

At t=10 CLILDAA #$78ADDA #$44

A device requests an interrupt

(service)

Request is “masked”

CLI enables the IRQ

ISR runs ISR ACKs the request, and in turn, the device

removes its request.

ISR completes, the state is restored, and the interrupted

program resumes @ ADDA #$44.

This instruction is interrupted, and the state of the program at this

point is saved on the stack

19

TYPES OF INTERRUPTS for the Basic μP

• Interrupt Request (IRQ)

• Software interrupt (SWI)

• Non-maskable Interrupt (NMI)

• Reset

20

Vector Table

VectorAddress

Vector:Address of Routine

LOCATION OF INTERRUPT VECTORSVector Table

21

INTERRUPT VECTORS• FFF8 is the address of the Interrupt Request (IRQ) vector. The content of

FFF8:FFF9 is the address of the IRQ routine, i.e., the address of the first instruction of the IRQ routine.

• FFFA is the address of the Software Interrupt (SWI) vector. The content of FFFA:FFFB is the address of the SWI routine, i.e., the address of the first instruction of the SWI routine.

• FFFC is the address of the Non-Maskable Interrupt (NMI) vector. The content of FFFC:FFFD is the address of the NMI routine, i.e., the address of the first instruction of the NMI routine.

• FFFE is the address of the Reset (RESET) vector. The content of FFFE:FFFF is the address of the RESET routine, i.e., the address of the first instruction of the RESET routine.

22

INTERRUPT REQUEST

(IRQ)

BasicμP

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Complete current

instruction

When this low signal reaches the IRQn pin:

then

23

SOFTWARE INTERRUPT

(SWI)

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24

• The software interrupt (SWI) is an instruction that can be placed anywhere within a program.

• It forces the μP to act as though an interrupt had occurred.

• When encountered within a program, the SWI causes the registers to be stacked and the starting address of the SWI service routine to be loaded into the PC, i.e., PC ← (FFFA:FFFB).

25

• SWI can be used to provide a method by which a user program can pass control back to an operating system.

• The address at (FFFA:FFFB) is the address of the SWI routine, which is part of the operating system.

• In this way, when a SWI interrupt occurs, the μPswitches to execute instructions of the OS program, and hence the OS takes control of the system.

• The OS can then chose to run another program, and thereby implement multitasking, for example.

26

NON-MASKABLE INTERRUPT

(NMI)

BasicμP

BasicμP

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27

• The non-maskable interrupt functions the same as the IRQ, except, the NMI is not masked.

• Note the test for the I bit is not present in stage (2) of the NMI automatic micro-operation processing.

• The NMI is used by devices requiring the μP’simmediate attention, and their request should never be ignored.

28

• An NMI can be used in a power failure detection circuit.

• In the event of a power failure, any important sources of information, such as the data in the internal MPU registers or some locations in external memory, must be preserved.

• When the power begins to fail, the detection circuit could generate an NMI signal, whereupon the μP would execute the NMI service routine.

• This NMI routine would save all of the important data in battery powered RAM before the power completely fails.

• When power is restored, a special flag in battery powered RAM would cause the RESET routine to restore the important information, and continue with the program that was interrupted by the power failure.

29

BasicμP

Micro-operationsPerformed when a RESET is sensed.

30

• The RESET routine is normally executed when the system powers up.

• System power up is achieved by a switch that turns the power on to the system, and causes a momentary pulse on the RESET pin of the μP.

• In addition, while the system is powered up, a push button switch can be used to cause the RESET routine to run, which would “reset” the processor.

• Note: in the lab, the reset is asserted when you run your program initially. Note the “Entry” label, and placement into the RESET vector location.

31

USING THE INTERRUPT METHOD OF I/O1. System is switched on, i.e., RESETn is asserted (momentary pulse).

2. μP executes the RESET mops, as shown on Slide 28, as follows:I-bit in the CCR is setPC ← (FFFE:FFFF)Main runs

3. After the program executes initialization routines, the I mask is cleared by the instruction CLI, and then the μP executes the loop.

4. At some time, the I/O Device 1 requests service by asserting the RFS signal.

5. Interface Adapter 1 senses the RFS, and in response the Interface Adapter 1 pulls IRQn low.

μPAddress Data Control

8

AB

US

DB

US

CB

US

I/O Device

18

DataRegister

Request For Service (RFS)

IRQ

PowerOn/Reset Circuit

RESET

8 512x8 ROM

Main_LBMain_HB

isrD1_LBisrD1_HB FFF8

FFF9

FFFEFFFF

A8-A0

Other Memories

Main lds #SS… ;initcli

loop ldaa #$7F…bra loop

isrD1 “Service D1”…rti

6. μP hardware senses IRQn low, and in response the μP hardware executes the IRQ mops, Slide 21.

…PC ← (FFF8:FFF9)

7. μP software executes the isrD1 routine.

8. On completion of the isrD1 routine, RTI is executed; this un-stacks the context of the machine, and the μP continues executing the loop in Main with the instruction following the one that was interrupted.

Interface Adapter 1

StatusRegisterControlRegister