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  • 1. Reg. No. : M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010 Elective VLSI Design VL 9261 ASIC DESIGN (Common to M.E. Applied Electronics and M.E. Computer & Communication) (Regulation 2009) Time : Three hours Maximum : 100 Marks Answer ALL questions PART A (10 2 = 20 Marks) 1. List the important features of Gate Array-Based ASICS. 2. What is the advantage of based design rule? 3. Compare antifuse, SRAM, EPROM and EEPROM technologies with respect to erasing mechanism. 4. Define CRITt . 5. List the different features of XILINX LCA interconnect architecture. 6. What do you understand by the term Half Gate ASIC? 7. State the function of IDDQ test. 8. Differentiate between physical faults and logical faults. 9. List any four issues that are to be considered when partitioning a complex system into custom ASICs. 10. Name the goals and objectives of detailed routing. Question Paper Code : 980884 0 1 4 0 1 4 0 1

2. 980882 PART B (5 16 = 80 Marks) 11. (a) Discuss the different types of ASICs with neat sketches. (16) Or (b) (i) Explain the Data path logic for a full adder along with different data path elements to be used in the design. (8) (ii) How do transistor resistance, parasitic capacitance and load capacitance affect the logic cell delay in ASICs? Explain. (8) 12. (a) (i) With a neat sketch explain the programming of Antifuse. What are its advantages and disadvantages? (8) (ii) What are the bench mark circuits proposed by PREP for the selection of programmable ASICs? (8) Or (b) (i) Draw and explain the features of XILINX 3000 CLB and the different types of interconnections. (10) (ii) What are the various ac and dc issues common to FPGA I/O cell design? (6) 13. (a) (i) Draw the interconnect architecture used in Actel ACT and discuss the routing process. (10) (ii) Explain the EDIF standard and write an EDIF net list for an example circuit. (6) Or (b) (i) Discuss the different parasitic capacitances that contribute to interconnect delay in XILINX LCA array. (10) (ii) Explain the various steps involved in the schematic design entry for ASICs. (6) 4 0 1 4 0 1 4 0 1 3. 980883 14. (a) (i) Write the VHDL code for a 8 bit ripple carry adder using full adder as a component. (8) (ii) Enumerate on the various operators used in Verilog. (8) Or (b) (i) Write a note on package and libraries of VHDL. (8) (ii) With example explain how Verilog is used to define delays. (8) 15. (a) (i) What are different methods available for testing ASICs and explain the BIST technique in detail. (8) (ii) Discuss the different methods of partitioning with relevant sketches. (8) Or (b) (i) Explain the procedure for measurement of delay in floor planning. (8) (ii) Draw and explain how global routing is established between and inside blocks. (8) 4 0 1 4 0 1 4 0 1