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23
I Appendix Appendix A: Modulus Margin M and Delay Margin ∆τ Fig. A-1 shows the relation modulus margin M and phase margin ∆τ. the modulus margin M is defined as the radius of the circle centered in 1, 0 j and tangent to the Nyquist plot of the system open-loop transfer function yy L , i.e. the minimum distance of yy L with respect to the critical locus (-1) in the Nyquist plan. From the definition, it results that min 1 j yy M L e (A.1) Substituting equation (4.3) into (A.1), 1 1 1 min max j yy j yy yy M S e S S e (A.2) As a consequence, the reduction (or minimization) of max j yy S e will imply the increase (or maximization) of the modulus margin M . -1 1 M Re H Im H Crossover frequency cr Fig. A-1 Modulus, gain, and phase margin From equation (A.2), it can be seen that the modulus margin M is equal to the inverse of the maximum of the modulus of the output sensitivity function 1 yy S z , i.e. the inverse of the H norm of 1 yy S z . The modulus margin is very important because [I2, I3, I4]: • It defines the maximum admissible value for the modulus of the output sensitivity function yy S . • It gives a bound for the characteristics of the nonlinear and time-varying elements tolerated in the closed-loop system (it corresponds to the circle criterion for the stability of nonlinear systems).

Transcript of Appendix Im H - INSA de Lyoncsidoc.insa-lyon.fr/these/2009/guo/15_appendix.pdf · Fig. D-1...

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Appendix

Appendix A: Modulus Margin ∆M and Delay Margin ∆τ

Fig. A-1 shows the relation modulus margin M and phase margin ∆τ. the modulus

margin M is defined as the radius of the circle centered in 1, 0j and tangent to the

Nyquist plot of the system open-loop transfer function yyL , i.e. the minimum distance of

yyL with respect to the critical locus (-1) in the Nyquist plan. From the definition, it results

that

min 1 j

yyM L e (A.1)

Substituting equation (4.3) into (A.1),

1 1 1min

max

j

yy jyyyy

M S eSS e

(A.2)

As a consequence, the reduction (or minimization) of max

j

yyS e will imply the increase (or

maximization) of the modulus margin M .

-1 1

M Re H

Im H

Crossover

frequency

cr

Fig. A-1 Modulus, gain, and phase margin

From equation (A.2), it can be seen that the modulus margin M is equal to the inverse of

the maximum of the modulus of the output sensitivity function 1

yyS z , i.e. the inverse of the

H norm of 1

yyS z . The modulus margin is very important because [I2, I3, I4]:

• It defines the maximum admissible value for the modulus of the output sensitivity

function yyS .

• It gives a bound for the characteristics of the nonlinear and time-varying elements tolerated

in the closed-loop system (it corresponds to the circle criterion for the stability of nonlinear

systems).

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The delay margin is the additional delay which will make the closed-loop system

unstable. It is deduced from the phase margin and can be computed as follows:

cr

(A.3)

where cr is the crossover frequency (see Fig. A-1 where the Nyquist plot intersects the unit

circle).

If the Nyquist plot intersects the unit circle at several frequencies, i

cr , characterized by the

corresponding phase margin i , then the delay margin is defined by the minimum value:

min i

i

cr

(A.4)

This situation appears systematically for systems with multiple vibration modes or with pure

time delays.

In order to ensure robustness, the modulus margin M is kept higher than 0.5 and the delay

margin must be higher than the switching period sT (to ensure that the delay induced by

controller computing time does not lead to unstable operation). Generally the typical values of

these robustness margins for a “robust” controller design are [I2, I3, I4]:

• Modulus margin: 0.5M .

• Delay margin: sT .

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Appendix B: Small Signal and State-Space Averaging

A general method for describing a circuit which changes over a switching period is called

state-space averaging. The technique requires two sets of state equations which describe the

circuit: one set for the closed switch and another one set for the open switch. These state

equations are then averaged over the switching period. A state variable description of a

system is of the form:

T

x Ax Bv

y C x (B.1)

The state equations for a switched circuit with two resulting topologies are as follows (with

the assumption of continuous current mode):

1 1 2 2

1 2

T T

Closed Switch Open Switch

x A x B u x A x B u

y C x y C x

(B.2)

For the closed switch for the time dT and open for 1 d T , the previous equations have a

weighted average of

1 2 1 2

1 2

1 1

1T T

x A d A d x B d B d u

y C d C d x

(B.3)

Therefore, an averaged state-variable description of the system is described as in the general

form of Equation (B.1) with

1 2

1 2

1 2

1

1

1T T T

A A d A d

B B d B d

C C d C d

(B.4)

Small signal and steady-state analyses of the system are separated by assuming that the

variables are perturbed around the steady-state operating point. Namely,

x X x

d D d

u U u

(B.5)

where X, D, and U represent steady-state values, x , d and u represent small signal values.

For the steady state, 0x and the small signal values are zero. Equation (B.1) becomes 1

10

T

X A BUAX BU or

Y C A BU (B.6)

where the matrices are the weighted averages of Eq. (B.4).

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The small signal analysis starts by recognizing that the derivative of the steady-state

component is zero:

0x X x x x (B.7)

Substituting steady-state and small signal quantities into Eq. (B.3),

1 2 1 21 1x A D d A D d B D d B D d U u (B.8)

If the products of small signal terms x d can be neglected, and if the input is assumed to be

constant,u U , i.e. 0u , then the small signal output values

1 2 1 2 1 2

1 2 1 2

1

1T T T T

x A D A D x A A X B B U d

y C D C D x C C X d

(B.9)

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Appendix C: State-Space Averaging for Buck Converter

State-space averaging is useful for developing transfer functions for switched circuits such

as DC-DC converters. The buck converter is used in this work. State equations for the closed

switch are developed from Fig. C-l (a), and state equations for the open switch are from Fig.

C-l (b).

Vin

LRL

R

outV

LiRiCi

CVC

CR

+

-

LRL

R

outV

LiRiCi

CVC

CR

+

-

(a) (b) Fig. C-1 Circuits for developing the state equations for the buck converter:

(a) Closed switch, (b) Open switch

Closed Switch: First the state equations for the buck converter (also for the forward converter)

are determined for the closed switch. The outermost loop of the circuit in Fig. C-l (a) has the

Kirchhoff's voltage law equation:

LL L L in

diL i R i r V

dt (C.1)

Kirchhoff's current law gives

CR L C L

dVi i i i C

dt (C.2)

Kirchhoff's voltage law around the left inner loop gives

LC C C in

diL i r V V

dt (C.3)

which gives the relation

1C CC in C

C

dV dVi C V L V

dt r dt (C.4)

Combining Equation (C.1) through (C.4) gives the state equation

1L CLL C in

C C

R r rdi Ri V V

dt R r L R r L L (C.5)

Kirchhoff's voltage law around the right inner loop gives

0C C C RV i r i R (C.6)

Combining the previous equation with Equation (C.2) gives the state equation

1CL C

C C

dV Ri V

dt C R r C R r (C.7)

Restating Equation (C.5) and (C.7) in state-variable form,

1 1 inx A x BV (C.8)

where

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1 1

1

, , 1

0

L C

L C C

C

C C

R r r R

i R r L R r Lx A B L

RV

C R r C R r

(C.9)

Open Switch: The filter is the same for the closed switch as for the open switch. The input to

the filter is zero when the switch is open and the low-side Mosfet is conducting. State

equation (C.1) is modified accordingly, resulting that Equation (D.5) changes as

0L CL

L C

C C

R r rdi Ri V

dt R r L R r L (C.10)

The Kirchhoff's voltage law around the right inner loop maintains the same in Eq. (C.7)

1CL C

C C

dV Ri V

dt C R r C R r (C.11)

Therefore, the matrix 2A and 2B during the “open” period are respectively:

2 1 2 , 0A A B (C.12)

Weighting the state variables over one switching period gives

1 1

2 21 1 1

in

in

x d A xd BV d

x d A x d B V d

(C.13)

Adding the previous equations and using 2 1A A and 2 0B ,

1 1 inx A x BV d (C.14)

In detailed form,

1

10

L C

L C C L

in

CC

C C

R r r R

i R r L R r L ix VL

VRV

C R r C R r

(C.15)

Equation (C.15) gives the averaged state-space description of the output filter and load of the

buck converter.

The output voltage outV , is determined from

out Cout R L C L

C

V VV Ri R i i R i

r (C.16)

Rearranging to solve for outV ,

Cout L C

C C

Rr RV i V

R r R r (C.17)

The previous output equation (C.17) is valid for both closed and open switch positions in

CCM, resulting in 1 2

T T TC C C . In state-variable form, T

outV C x (C.18)

where

LT C

CC C

iRr RC and x

VR r R r (C.19)

The steady-state output is found from Eq. (A.6)

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1T

out inV C A BV (C.20)

where 1 2A A A , 1B B D , and 1 2

T T TC C C . The final result of this computation results

in a steady-state output of

out inV V D (C.21)

The small signal transfer characteristic is developed from Eq. (A.9), which in the case of the

buck converter results in

inx A x BV d (C.22)

Taking the Laplace transform,

ins x s A x s BV d s (C.23)

Grouping x s ,

insI A x s BV d s (C.24)

where I is the identity matrix. Solving for x s ,

1

inx s sI A BV d s (C.25)

Expressing outV in term of x s ,

1T T

out inV s C x s C sI A BV d s (C.26)

Finally, the transfer function of output to variations in the duty ratio is expressed as

1out T

in

V sC sI A BV

d s

(C.27)

Upon substituting for the matrices in the previous equation, a lengthy evaluation process

results in the transfer function

2

ˆ ( 1)

ˆ (1 ) ( ) 1

out C in

C L C L C L

V s sR C V

s R R LC s R C R C R R C R L R R Rd s (C.28)

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Appendix D: Schematic Circuit of Buck Converter

Fig. D-1 Schematic Circuit of Prototype Buck Converter

Appendix E: Schematic Circuit of A/D Converter

Fig. E-1 Schematic Circuit of Prototype A/D Converter

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Appendix F: Top-Level VHDL Code for Digital Controller

Three full digital controllers, PID, RST and SMC, are respectively applied in this work.

Except the algorithm part, all other parts (such as voltage reference slope function, system

multiplex clocks, digital filter of A/D values, interface button input function, dynamic load

switch, external LEDs monitoring, etc) are the same for each digital controller, i.e., these

digital controllers are very similar in VHDL architecture design.

Due to page limit, here we just take the Top-level Architecture (Components Mapping) of

Sliding-Mode Controller for an instance. The detailed HDL codes and schematic files of each

component are not illustrated here.

Top-level Architecture for Sliding-mode Controller:

---------------------------------------------------------------------------------------------------------------------------------

-- Company: AMPERE-INSA-LYON

-- Author: Shuibao GUO

-- Create Date: 17:12:51 19/03/2008

-- Design Name: Sliding_Mode_Control_4MHz

-- Module Name: Top_Level_Sliding_Mode

-- Project Name: ADC10bit_DPWM11bit_Sliding_Mode_Control_4MHz

-- Target Devices: XC2VP30 Xilinx

-- Tool versions: ISE9.2i

-- Description: Digital control for high frequency SMPS

-- Revision: V1.0

-- Revision 0.01 - File Created

-- Additional Comments:

---------------------------------------------------------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

--Uncomment the following library declaration if instantiating

--any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

------------------------------------------------------------------------------

Entity test_Sliding_Mode_ADC10bit_PWM11bit is

Port ( REST_system : in STD_LOGIC; -- %system input rest

clk_32M : in STD_LOGIC; -- %system input clock

button_start : in STD_LOGIC; -- %system button „start‟

button_stop : in STD_LOGIC; -- %system button „stop‟

button_SW1 : in STD_LOGIC; -- %load change button 1 => (5Ohm to 3.3Ohm)

button_SW2 : in STD_LOGIC; -- %load change button 2 => (3.3Ohm to 2.5Ohm)

button_CANCEL : in STD_LOGIC; -- %system button „pause‟

data_AD : in STD_LOGIC_VECTOR (9 DOWNTO 0); --%ADC 10-bit

pwm1 : out STD_LOGIC; -- %Nmos

pwm2 : out STD_LOGIC;-- %Pmos

Switch1 : out STD_LOGIC;-- %load variation 1

Switch2 : out STD_LOGIC; -- %load variation 2

clk_AD : out STD_LOGIC; -- %AD sampling clock (16MHz)

LED_clk_ready : out STD_LOGIC;-- %LED indicator for DCM clock

LED_system_on : out STD_LOGIC; -- %LED indicator for power supply

LED_vref_slope : out STD_LOGIC; -- %LED indicator for Vref slope action

LED_power_charge: out STD_LOGIC -- %LED indicator for charge and discharge in buck converter

);

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end test_ Slidng_Mode _ADC10bit_PWM11bit;

------------------------------------------------------------------------------

architecture Behavioral of test_Sliding_ADC10bit_PWM11bit is

------------------

SIGNAL REST : STD_LOGIC; --% reset

SIGNAL DCM1_RST : STD_LOGIC; --% DCM1 reset

SIGNAL DCM2_RST_TEMP : STD_LOGIC; --% DCM2 temporary reset

SIGNAL DCM2_RST : STD_LOGIC; --% DCM2 reset

SIGNAL DCM3_RST : STD_LOGIC; --% DCM3 temporary reset

SIGNAL DCM3_RST_TEMP : STD_LOGIC; --% DCM3 reset

SIGNAL DCM4_RST : STD_LOGIC; --% DCM4 temporary reset

SIGNAL DCM4_RST_TEMP : STD_LOGIC; --% DCM4 reset

SIGNAL LOCKED_OUT1 : STD_LOGIC; --% DCM1 output locked

SIGNAL LOCKED_OUT2 : STD_LOGIC; --% DCM2 output locked

SIGNAL LOCKED_OUT3 : STD_LOGIC; --% DCM3 output locked

SIGNAL LOCKED_OUT4 : STD_LOGIC; --% DCM4 output locked

SIGNAL clk_16M : STD_LOGIC; --%16MHz

SIGNAL clk_32M : STD_LOGIC; --%32MHz

SIGNAL clk_64M : STD_LOGIC; --%64MHz

SIGNAL clk_128M : STD_LOGIC; --%128MHz

SIGNAL CLK0_temp : STD_LOGIC; --%CLK 0 degree

SIGNAL CLK90_temp : STD_LOGIC; --%CLK 90 degree

SIGNAL CLK180_temp : STD_LOGIC; --%CLK 180 degree

SIGNAL CLK270_temp : STD_LOGIC; --%CLK 270 degree

SIGNAL Clk_16M_Sys : STD_LOGIC; --%System CLK 16MHz

SIGNAL Clk_32M_Sys : STD_LOGIC; --%System CLK 32MHz

SIGNAL Clk_64M_Sys : STD_LOGIC; --%System CLK 64MHz

SIGNAL Clk_128M_Sys : STD_LOGIC; --%System CLK 128MHz

SIGNAL High_Volage : STD_LOGIC; --%VCC=3.3V

SIGNAL Low_Volage : STD_LOGIC; --%GND=0V

SIGNAL sc_select : STD_LOGIC; --%sc from DCM

SIGNAL system_on : STD_LOGIC; --%system „on‟ indicator

SIGNAL power_on : STD_LOGIC; --%charge „on‟ indicator for buck converter

SIGNAL operate_pwm : STD_LOGIC; --% open-loop or closed-loop test flag

SIGNAL pwm_inc : STD_LOGIC; --% increase pwm duty ratio in open-loop

SIGNAL pwm_dec : STD_LOGIC; --% descrease pwm duty ratio in open-loop

SIGNAL vref_flag : STD_LOGIC; --% flag in slope function for Vref

SIGNAL power_flag : STD_LOGIC; --% LED „on‟ when charge

SIGNAL Vref_voltage : STD_LOGIC_vector(9 downto 0);--%Vref in 10-bit

SIGNAL pwm_duty : STD_LOGIC_vector(10 downto 0); --%DPWM duty in 11-bit

SIGNAL pwm_core_duty : STD_LOGIC_vector(5 downto 0); --%DPWM hardware duty in 6-bit

SIGNAL pwm_count : STD_LOGIC_vector(1 downto 0); --%2-bit counter comparator in DPWM

SIGNAL pwm_seg_dcm : STD_LOGIC_vector(3 downto 0);-- %4-bit segmented DCM in DPWM

SIGNAL load_switch : std_logic;--%flag for transient load

SIGNAL data_average : STD_LOGIC_vector(9 downto 0);-- filter of ADC data

------------------

component DPWM128M_Application is --%generate system clocks 16M, 32M, 64M and 128M

port(clk_IN_32M : in std_logic;

REST_in : in std_logic;

LOCKED : out std_logic;

clk_AD_16M : out std_logic;

CLK_SYS_16M : out std_logic

CLK_SYS_32M : out std_logic

CLK_SYS_64M : out std_logic

sc : out std_logic CLK_SYS_128M : out std_logic

);

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end component;

------------------

component CLK_ACCOUNT is --%PWM 2-bit counter

Port ( clk : in STD_LOGIC;

rest : in STD_LOGIC;

sc : in STD_LOGIC;

E : in STD_LOGIC;

clk_account: out STD_LOGIC_vector(1 downto 0)

);

end component;

------------------

COMPONENT Scan_key_START_STOP is --% system button deal

Port ( rest : in STD_LOGIC;

C lk : in STD_LOGIC;

button_stop : in STD_LOGIC;

button_start : in STD_LOGIC;

system_status : out STD_LOGIC

);

end COMPONENT;

------------------

COMPONENT PWM_out_without_dead_time is --% output DPWM

Port ( rest: in STD_LOGIC;

clk : in STD_LOGIC;

E : in STD_LOGIC;

clk_account : in STD_LOGIC_VECTOR(1 downto 0);

pwm_value : in STD_LOGIC_VECTOR(1 downto 0);

power_flag : out STD_LOGIC;

pwm1 : out STD_LOGIC;

pwm2 : out STD_LOGIC;

power_on : out STD_LOGIC

);

end COMPONENT;

------------------

COMPONENT Vref_Slope_Function is --%slope function for Vref

Port ( rest : in STD_LOGIC;

clk : in STD_LOGIC;

E : in STD_LOGIC;

Vref_flag : out STD_LOGIC;

Vref : out STD_LOGIC_VECTOR (9 downto 0));

end COMPONENT;

------------------

COMPONENT Algorithm_sliding is --%Sliding Mode Control Algorithm

port( rest : in std_logic;--system Rest

--% clk : in std_logic;--clock input is 32MHz --%calculation clock can be changed one of three

--% clk : in std_logic;--clock input is 64MHz

clk : in std_logic;--clock input is 128MHz

E : in std_logic;--system on

load_change : in std_logic;--transient load

clk_account : in std_logic_vector(4 downto 0);

Vref_given : in std_logic_vector(9 downto 0);

din : in std_logic_vector(9 downto 0);

pwm_value : out STD_LOGIC_VECTOR(4 downto 0)

);

end COMPONENT;

------------------ COMPONENT Output_LED is --% LED indicators

Port ( rest : in STD_LOGIC;

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clk : in STD_LOGIC;

E : in STD_LOGIC;

power_on : in STD_LOGIC;

clk_LOCKED : in STD_LOGIC;

slope_flag : in STD_LOGIC;

LED_clk_ready : out STD_LOGIC;

LED_system_on : out STD_LOGIC;

LED_vref_slope : out STD_LOGIC;

LED_power_charge : out STD_LOGIC

);

end COMPONENT;

------------------

COMPONENT Deal_key_Switch is --% system buttons deal

Port ( rest : in STD_LOGIC;

clk : in STD_LOGIC;

E : in STD_LOGIC;

button_SW1 : in STD_LOGIC;

button_SW2 : in STD_LOGIC;

button_CANCEL : in STD_LOGIC;

load_transient : out std_logic;--transient load

SW1 : out STD_LOGIC;

SW2 : out STD_LOGIC

);

end COMPONENT ;

------------------

COMPONENT AD_Filter is --%ADC filter

Port ( clk : in STD_LOGIC;

rest : in STD_LOGIC;

data_in : in STD_LOGIC_VECTOR (9 downto 0);

data_out : out STD_LOGIC_VECTOR (9 downto 0)

);

end COMPONENT ;

--====================================================================

begin

---------------------------------------

High_Volage<='1';

Low_Volage<='0';

-----------------------------------------

Inst_Clocking:DPWM128M_Application PORT MAP( --%inst DCM block

clk_IN_32M => clk_32M,

REST_in=> REST_system,

clk_AD_16M=>clk_AD,

sc=>sc_select,

LOCKED=>LOCKED_OUT3,

clk_SYS_128M=>clk_128M_Sys,

clk_SYS_64M=>clk_64M_Sys

clk_SYS_32M=>clk_32M_Sys,

clk_SYS_16M=>clk_16M_Sys

);

-----------------------------------------

Inst_clk_count: CLK_ACCOUNT PORT MAP(--%inst counter comparator

clk => clk_128M_Sys,

rest =>REST_system,

E => system_on,

sc=>sc_select, clk_account => pwm_count

);

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------------------------------------------%Scan Up and Down key to Start or Close system

Inst_System_ON_OFF: Scan_key_START_STOP Port MAP(

clk => clk_128M_Sys,

rest =>REST_system,

button_stop => button_stop,

button_start => button_start,

system_status => system_on

);

-----------------------------------------%set the vref slope function

Inst_Slope_Function: Vref_Slope_Function Port MAP(

clk => clk_128M_Sys,

rest =>REST_system,

E => system_on,

Vref_flag => vref_flag,

Vref => Vref_voltage

);

---------------------------------------

Inst_Algorithm_sliding: Algorithm_sliding Port MAP( --% inst SMC algorithm

clk => clk_128M_Sys, --%select one clock of three

--% clk => clk_64M_Sys,

--% clk => clk_32M_Sys,

rest =>REST_system,

E => system_on,

load_change=>load_switch,

clk_account => pwm_count,

Vref_given => Vref_voltage,

din => data_average, --for 10bit, AD_Filter is selected

--din => data_AD(9 downto 0), --for 10bit, AD_Filter is not selected

pwm_value => pwm_value

);

------------------------------------------%Output PWM

Inst_Output_PWM: PWM_out_without_dead_time port MAP(

clk => clk_128M_Sys,

rest =>REST_system,

E => system_on,

clk_account=>pwm_count,

pwm_value => pwm_seg_dcm, -- use control law

--pwm_value =>"100000", -- for open loop test in hardware DPWM

power_flag =>power_flag,

pwm1 =>pwm1,

pwm2 =>pwm2,

power_on =>power_on

);

------------------------------------------%Output relative LED

Inst_Output_LED: Output_LED Port MAP(

clk => clk_128M_Sys,

rest =>REST_system,

E =>system_on,

power_on =>power_on,

slope_flag =>vref_flag,

clk_LOCKED =>LOCKED_OUT3,

LED_clk_ready =>LED_clk_ready,

LED_system_on =>LED_system_on,

LED_vref_slope =>LED_vref_slope,

LED_power_charge =>LED_power_charge );

---------------------------------------------------------------------

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XIV

Inst_Road_Switch: Deal_key_Switch Port MAP(--%load variation button deal

clk => clk_128M_Sys,

rest =>REST_system,

E =>system_on,

button_SW1 => button_SW1,

button_SW2 => button_SW2,

button_CANCEL => button_cancel,

load_transient => load_switch,--transient load

SW1 => Switch1,

SW2 => Switch2

);

---------------------------------------------------------------------

Inst_AD_Filter: AD_Filter Port MAP(--%ADC data filter

clk => clk_128M_Sys,

rest =>REST_system,

data_in =>data_AD,

data_out =>data_average

);

--====================================================================

end Behavioral;

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XV

Appendix G: Test of PID and RST at Switching Frequency 1MHz

Parameters of RST controller at 1MHz:

0 1 1 2 2 3 3

0 1 1 2 2

1 1 2 2

-

-

u k T w k T w k T w k T w k

R y k R y k R y k

S u k S u k

where

2

2

3 2

( ) 27.0362 48.3568 21.8616

( ) 1.05040 0.05050

( ) 48.6219 116.4903 93.1598 24.7504

R z z z

S z z z

T z z z z

Parameters of PID controller at 1MHz:

0 1 1 2 2 1 1 2 2d k R e k R e k R e k S d k S d k

where

2

2

( ) 40.2481 78.5639 38.5882

( ) 1.1647 0.1647

R z z z

S z z z

101

102

-40

-35

-30

-25

-20

-15

-10

-5

0

5

f [KHz]

S [

dB

]

PID Syy

RST Syy

-10dB

Fig. G-1 Syy sensibility function for RST and PID controllers at 1MHz

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XVI

Fig. G-2 Mosfet driver signal of PID Control Fig. G-3 Mosfet driver signal of RST Control

Fig. G-4 High-side Mosfet driver signal and Vout Fig. G-5 High-side Mosfet driver signal and Vout

of PID controller of RST Control

Fig. G-6 transient Vout of PID when load Fig. G-7 transient Vout of RST when load

goes from 0.3A to 0.46A (R: 5Ω→3.3Ω) goes from 0.3A to 0.46A (R: 5Ω→3.3Ω)

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XVII

Appendix H: Test of PID and RST at Switching Frequency 2MHz

Parameters of RST controller at 2MHz:

0 1 1 2 2 3 3

0 1 1 2 2

1 1 2 2

-

-

u k T w k T w k T w k T w k

R y k R y k R y k

S u k S u k

where

2

2

3 2 1

( ) 48.8953 90.9579 42.3798

( ) 1.3755 0.3756

( ) 126.5058 327.7569 283.0460 81.4776

R z z z

S z z z

T z z z z

Parameters of PID controller at 2MHz:

0 1 1 2 2 1 1 2 2d k R e k R e k R e k S d k S d k

where

2

2

( ) 56.2966 111.3238 55.1235

( ) 1.5610 0.5610

R z z z

S z z z

101

102

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

f [KHz]

S [

dB

]

PID Syy

RST Syy

-15dB

Fig. H-1 Syy sensibility function for RST and PID controllers at 2MHz

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XVIII

Fig. H-2 Mosfet driver signal of PID Control Fig. H-3 Mosfet driver signal of RST Control

Fig. H-4 High-side Mosfet driver signal and Vout Fig. H-5 High-side Mosfet driver signal and Vout

of PID controller of RST Control

Fig. H-6 transient Vout of PID when load Fig. H-7 transient Vout of RST when load

goes from 0.3A to 0.46A (R: 5Ω→3.3Ω) goes from 0.3A to 0.46A (R: 5Ω→3.3Ω)

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XIX

Appendix I: Test of Tri-Mode at 1MHz and Switching Frequency 2MHz

Fig. I-1 transient Vout of Tri-Mode Control at 1MHz when load goes from 0.3Ato 0.46A (R: 5Ω→3.3Ω)

Fig. I-2 transient Vout of Tri-Mode Control at 2MHz when load goes from 0.3Ato 0.46A (R: 5Ω→3.3Ω)

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XX

Appendix J: Test of Sliding-Mode at Switching Frequency 1MHz and 2MHz

Fig. J-1 Mosfet driver signal of SMC Fig. J-2 Mosfet driver signal of SMC

operating at 1MHz operating at 2MHz

Fig. J-3 High-side Mosfet driver signal and Vout Fig. J-4 High-side Mosfet driver signal and Vout

of SMC operating at 1MHz of SMC operating at 2MHz

Fig. J-5 transient Vout of SMC operating at 1MHz Fig. J-6 transient Vout of SMC operating at 2MHz

when load goes from 0.3A to 0.46A (R: 5Ω→3.3Ω) when load goes from 0.3A to 0.46A (R: 5Ω→3.3Ω)

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XXI

Appendix K: Information about IC Design of the Digital Controller

As the preliminary research work, the proposed digital controllers only have been

implemented in FPGA to validate the design functionality, and the subsequent project to

implement the digital controller on a 0.35µm CMOS ASIC has started lately. The IC layouts

of PID and RST controller have been accomplished, and the implementation of SMC is

under process. The prepared layouts have been delivered to IC fabrication, and the chips will

be available after April 2009. Here are some information about the digital controller IC

design.

The IC design follows the top-down design flow in the digital integrated-circuit. The

design procedure and verification task involves the flowing tools:

1. Modesim ver5.8c (Mentor)

2. Buildgates ver05.17 (Cadence)

3. Encounter ver6.2 (Cadence)

4. IC ver5.1.41 (Cadence)

5. Assura ver5.1.41 (Cadence)

The design flow is figured in Fig. K-1, where it includes the layout and the verification

implementation. Due to the lake of DMC module at present, the Hybrid ∆-Σ DPWM is

implemented as 6-bit ∆-Σ modulator and a 5-bit counter comparator. The layout of the RST,

PID and DPWM is shown in Fig. K-2, and the Pins location of the IC are detailed in Fig. K-3.

The characteristics of the IC are summarized in Table K-1. It is clear that the RST controller

consumes larger area than PID, which validates the description in Chapter3. From the

characteristics table, it can be seen that the proposed digital controller allows operation at

very-high switching frequencies and has very low power consumption. The precise energy

evaluation of the IC can be obtained only by the test on the final IC.

Table K-1 Parameters of chip-implementation for proposed digital controller

Module On-Chip Area Frequency range Power Current cons.

RST

PID

DPWM

2478476.00 µm2

1064081.18 µm2

98880.60 µm2

up to 21.92 MHz

up to 51.23 MHz

up to 98.04 MHz

2.3893 mW

0.7618 mW

0.0545 mW

33.03 µA/MHz

4.51 µA/MHz

0.17 µA/MHz

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XXII

RTL Simulation

(ModelSim)

Logic Synthesis

(Buildgates)

Contraints

Technology File

Other reports Timing Contraints Gate Level Netlist

Standard Cell Place and Route

(Encounter)

SDF Timing Data

VHDL Testbench Editing

(vi, nedit, emacs)

VHDL Source Code Editing

(vi, nedit, emacs)

Technology File

IO Constraint files

Gate Level Netlist

SDF Timing Data Layout file GDSII

Other reports

Post Process

(IC5.1.41) Stream In Out Map

Design Verification

(Assura) Design Rule

Parasitic Parameter Extraction

(Assura)

Post-layout Simulation

(Spectre)

Layout

Implementation

Layout

Verification

Fig. K-1 IC design flow of the digital controller

Fig. K-2 Layout of PID, RST and DPWM in a 0.35µm process

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XXIII

RST/ alpha6[BU12P]

RST/alpha4[BU12P]

RST/alpha0[BU12P]

RST/VDD[VDD3IP]

RST/REST[ICP]

RST/E[ICP]

RST/Vref_flag[BU12P]

PAD/VDD[VDD3OP]

RST/din1[ICP]

RST/din4[ICP]

RST/din6[ICP]

RST/din2[ICP]

RST/din7[ICP]

RST/din5[ICP]

RST/GND[GND3IP]

DPWM/alpha5[ICP]

DPWM/alpha10[ICP]

DPWM/alpha8[ICP]

DPWM/alpha0[ICP]

DPWM/alpha7[ICP]

DPWM/alpha6[ICP]

PAD/GND[GND3OP]

DPWM/alpha9[ICP]

DPWM/alpha4[ICP]

DPWM/E[ICP]

DPWM/PWM2[BU12P]

DPWM/CLK[ICCK12P]

DPWM/rest[ICP]

RS

T/a

lph

a2

[BU

12

P]

RS

T/a

lph

a1

[BU

12

P]

RS

T/a

lph

a10

[BU

12

P]

RS

T/a

lph

a7

[BU

12

P]

RS

T/a

lph

a3

[BU

12

P]

RS

T/a

lph

a9

[BU

12

P]

RS

T/a

lph

a5

[BU

12

P]

RS

T/a

lph

a8

[BU

12

P]

RS

T/C

LK

[IC

CK

16

P]

PID

/VD

D[V

DD

3IP

]

RS

T/d

in0[I

CP

]

PA

D/V

DD

[VD

D3

OP

]

PID

/CL

K[I

CC

K1

6P

]

PID

/E[I

CP

]

PID

/PW

M1

[BU

12

P]

PID

/po

wer_

on

[BU

12

P]

PID

/PW

M2

[BU

12

P]

DP

WM

/alp

ha2

[IC

P]

DP

WM

/alp

ha1

[IC

P]

DP

WM

/VD

D[V

DD

3R

P]

DP

WM

/alp

ha3

[IC

P]

RS

T/d

in 3

[ICP

]

RS

T/d

in 8

[ICP

]

RS

T/d

in 9

[ICP

]

PID

/din

2[IC

P]

PID

/ref_

sho

w[B

U1

2P

]

PID

/din

1[IC

P]

PID

/din

3[IC

P]

PID

/din

9[IC

P]

PID

/din

4[IC

P]

PA

D/V

DD

[VD

D3

OP

]

PID

/rest[IC

P]

PID

/ din

6[IC

P]

PID

/din

8[IC

P]

PID

/din

5[IC

P]

PID

/din

7[IC

P]

PID

/ GN

D[G

ND

3IP

]

PID

/din

0[IC

P]

DP

WM

/po

wer_

on

[BU

12

P]

DP

WM

/po

wer_

flag

[BU

12

P]

DP

WM

/GN

D[G

ND

3R

P]

DP

WM

/ pw

m1

[BU

12

P]

Fig. K-3 Pins distribution of the digital controller IC