# Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode · PDF file...

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M.H. Perrott

Analysis and Design of Analog Integrated Circuits Lecture 8

Cascode Techniques

Michael H. Perrott February 15, 2012

Copyright © 2012 by Michael H. Perrott All rights reserved.

M.H. Perrott

Review of Large Signal Analysis of Current Mirrors

M2M1

I1

Vdd

Vss=0

I2

VTH+ΔV1 VTH+ΔV2

Vds2 > Vdsat2

I2 μnCox

W2 L2

1 2 (VGS2-VTH)

2(1+λ2Vds2)

ΔV2

I1 μnCox W1 L1

1 2 (VGS1-VTH)

2(1+λ1Vds1)

ΔV1

=

ΔV1 = ΔV2But, VTH+ΔV1=VTH+ΔV2

I2 W2 L2

(1+λ2Vds2) I1 W1

L1 (1+λ1Vds1)

=

Mismatch due to Vds difference

Current setting

based on geometry

Note: for accurate ratio, set L1 = L2 Vds2

I2

Triode

Saturation

Vdsat2

M2 in

M2 in

2

M.H. Perrott

The Issue of Vds Mismatch in Current Mirrors

Issue: Current I2 can vary significantly as a function of the drain voltage of M2- We often want a tightly controlled current set only by I1

and transistor sizes How do we improve the current mirror matching

performance?

M2M1

I1

Vdd

I2

Vds2

I2 W2 (1+λ2Vds2)

I1 W1 (1+λ1Vds1) =

Mismatch

due to Vds difference

Current

setting

based on

geometry

Note: we are assuming L1 = L2 Vds1

3

M.H. Perrott

Cascoded Current Source

Offers increased output resistance - Reduces small signal dependence of output current on

the output voltage of the current source - From Lecture 6, we derived:

Output resistance boosted by intrinsic gain of M3, gm3ro3 But how do we reduce the influence of large signal Vds

mismatch between M1 and M2?

M1M2

Ibias

Iref

ro1

M3 Vbias

Rthd3

M3 Vbias

Rthd3

4

M.H. Perrott

Match Vds of Current Mirror Devices With Proper Bias

Key transistor for determining I2 is M1- Why is M2 less important? Above biasing approach provides a much closer

match between Vds1 and Vds4

I2 W1 L1

(1+λ1Vds1) I1 W4

L4 (1+λ4Vds4)

=

Mismatch due to Vds difference

Current setting

based on geometryM1

I1

Vdd

Vss=0

I2

VTH+ΔV

W/L

W/L

M2

VTH+ΔV VTH+ΔV

VTH+ΔV

W/L

W/L M4

M3 Vds2 > ΔV

Vds1 = VTH+ΔV

Vo Recall:

I2 = W1 W4

1 + λVds1 1 + λVds4

I1 ≈ W1 W4

I1 5

M.H. Perrott

The Drawback of Basic Cascode Bias Approach

Output voltage range is reduced - Now Vo must be > VTH + 2V- What will happen to the output impedance of the current

source if the output voltage is too low? - Can we improve the voltage range?

I2

V1

M1 and M2 in saturation

M1 and M2 in triode

M1

I1

Vdd

Vss=0

I2

VTH+ΔV

W/L

W/L

M2

VTH+ΔV VTH+ΔV

VTH+ΔV

W/L

W/L M4

M3 Vds2 > ΔV

Vds1 = VTH+ΔV VTH+2ΔV

M1 in saturation M2 in triode

Vo

Vo

calculation of V1 is nontrivial

6

M.H. Perrott

Improved Swing Cascode

Key idea: set size of M3 such that Vds1 = V- Assuming strong inversion for M1 and M3:

M1 and M2 in saturation

Vo

no wasted voltage region

I2

Vdsat1+Vdsat2

M1 and M2 in triode

M6

I1

Vdd

Vss=0 VTH+ΔV

αW/L

W/L

M5

VTH+2ΔV VTH+ΔV

VTH+ΔV

W/L

W/L

M4

M3

M1

I2

M2

VTH+ΔV

VTH+ΔV

W/L

W/L

Vds2 > ΔV

Vds1 = ΔV

Vo

2VTH+3ΔV

VTH+2ΔV

7

M.H. Perrott

Alternative Implementation of Improved Swing Cascode

Set as on previous slide Note: both implementations share a common problem

M1

I1

Vdd

Vss=0

I2

VTH+ΔV

αW/L

W/L

M2

VTH+2ΔV VTH+ΔV

VTH+ΔV

W/L

W/L M4

M3 Vds2 > ΔV

Vds1 = ΔV

Vo

M5 M6 M7 Wp/LpWp/LpWp/Lp

I1I1

M1 and M2 in saturation

Vo

no wasted voltage region

I2

M1 and M2 in triode

2ΔV

8

M.H. Perrott

The Issue of Current Mismatch

The improved swing approach causes a systematic mismatch between I2 and I1- Key issue: Vds1 Vds4

Can we fix this problem?

M1

I2

W/L

M2VTH+2ΔV

VTH+ΔV

M4 Vds1 = ΔV

I1

Vds4 = VTH+ΔV

I2 W2 (1+λ2Vds2) I1 W1 (1+λ1Vds1)

=

Mismatch due to Vds difference

W/L

Recall:

9

M.H. Perrott

Techniques to Reduce Current Mismatch

Systematic mismatch between I1 and I2 is greatly reduced by using the above circuit (now Vds1 ≈ Vds4)- Note that gate bias on M2 and M3 may be provided by

previously discussed circuits Additional techniques for accurately matching I1 and I2- Set L1 = L4 >> Lmin

Note: set L2 = L3 ≈ Lmin for lower area and capacitance- Set W2/W3 = I2/I1 so that V2 = V3

M1

I2

W/L

M2VTH+2ΔV

VTH+ΔV

M4 Vds1 = ΔV

I1

Vds4 = ΔV W/L

M3

VTH+ΔV

W/LW/L

10

M.H. Perrott

Another Common Cascode Bias Topology

Key issue: needs two bias current branches

M1

I2

W/L

M2

VTH+2ΔV

VTH+ΔV

M4 Vds1 = ΔVVds4 = ΔV

W/L

M3

VTH+ΔV

W/LW/LI1

Vdd

W/L M8

M5 M6 M7 Wp/LpWp/LpWp/Lp

I1I1

W/L

W/L

W/L

W/L

W/L

M9

M10

M11

M12

M13

11

M.H. Perrott

Utilizing a Simple Resistor to Achieve One Bias Branch

Issue: poly resistor is large and won’t track NMOS devices across temperature and process variations

M1

I2

W/L

M2

VTH+2ΔV

VTH+ΔV

M4 Vds1 = ΔVVds4 = ΔV

W/L

M3

VTH+ΔV

W/LW/LI1

M5 M7 Wp/LpWp/Lp

I1

RBΔV

12

M.H. Perrott

Better Approach: Use PMOS Device In Triode Region

Much smaller, better tracking with NMOS devices than resistor

M1

I2

W/L

M2

VTH+2ΔV

VTH+ΔV

M4 Vds1 = ΔVVds4 = ΔV

W/L

M3

VTH+ΔV

W/LW/LI1

M5 M7 Wp/LpWp/Lp

I1

ΔV M6

Wp/Lp

13

M.H. Perrott

Wilson Current Mirror

Relies on feedback in its operation Using Hybrid- analysis

- Output resistance comparable to cascode current source This circuit is rarely used these days

I1

M1

I2

M2

M3

Rthd2

14

M.H. Perrott

Enhanced Cascode Current Source

Offers output resistance comparable to double cascode current source

As with Wilson mirror, analysis is tricky due to source/gate coupling - Using results shown in the following slide:

M4

M3

M1M2

Ibias IrefIbias2

15

M.H. Perrott

Thevenin Resistances for CMOS Transistor Feedback Pair

RC

RB

-gmb4vs4vgs4

vs4

ro4gm4vgs4

RC

M4

M3

RA

RB

Rthd

Rths

Rthd

-gmb3vs3 vgs3ro3 gm3vgs3

RA

vs3=0

Rths

M4

M3

S

D

S

D

16

M.H. Perrott

Basic Cascode Amplifier

Allows improved frequency response (discussed later) Reduction to two-port will be done in several steps

Vout

RD

RG

Vin RS

Rthg1

RG

vin Av1vg1vg1

is1

RS

Rths1

Rthd11 is1α

g1

s1

d1

M1

M2

M1

is2Rths2

Rthd2 vout2is2α

s2

d2

M2

RD

Common Gate

General Model

17

M.H. Perrott

Eliminate Middle Sections

Calculation of Gm1 same as for common source amp To reduce further, note that

Vout

RD

RG

Vin RS

Rthg1

RG

vin vg1 Rthd1m1 vg1G

g1 d1

M1

M2

M1

is2Rths2

Rthd2 vout2is2α

s2

d2

M2

RD

18

M.H. Perrott

Resulting Two-Port Similar to Common Source Amp

Key difference: drain impedance much larger

Vout

RD

RG

Vin RS

Rthg1

RG

vin vg1

m1vg1G

g1

M1

M2

M1

Rthd2 vout

d2

M2

RD

19

M.H. Perrott

Slight Twist to Cascode Amplifier

What