Ελληνικός οδηγός Εγκατάστασης Ethernet και ασυρμάτου Δικτύου
An Extended-Range Ethernet and Clock Distribution Circuit for Distributed Sensor Networks
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An Extended-Range Ethernet and Clock Distribution Circuit for Distributed Sensor Networks Kael Hanson, Thomas Meures, Yifan Yang Interuniversity Insitute for High Energies (IIHE), Brussels Motivation : Detecting the GZK-flux ν EM cascade Radio-Cerenkov cone 37 stations Spacing: 2 km Depth under ice surface: 200 m Surface coverage: ~160 km 2 Ice thickness below: ~3000 m Each station: 16 + 4 sub-firn antennas (sensitive between 250 and 800 MHz): 8 vertically polarized 8 horizontally polarized 4 calibration pulsers (v-pol + h-pol) X surface antennas Hpol Quad-slot antenna VSWR < 3 above 300MHz p ARA (THE ASKARYAN RADIO ARRAY ) The GZK-mechanism as a “guaranteed” neutrino source: • Very few protons accelerated to UHE within GZK interaction length (most accelerators are further away from earth) • →GZK-mechanism should lead to cutoff in the UHECR spectrum • Cutoff confirmed by the Pierre AUGER Observatory Phys.Lett.B685:239-246, 2010 Detection method: • Emission of coherent radio waves from neutrino- induced EM-cascades (predicted by Askar’yan, 1962) • Verified at SLAC in 2007 Phys. Rev. Lett. 99, 171101, 2007 Reason: • Radio waves have long attenuation length in ice (~800m), large volumes with small number of antennas The ARA collaboration BELGIUM: Univ. Libre de Bruxelles. GERMANY: Univ. of Bonn, Univ. of Wuppertal. JAPAN: Chiba university. TAIWAN: National Taiwan Univ.. UNITED KINGDOM: Univ. College London. USA: Ohio State Univ., Univ. of Delaware, Univ. of Hawaii, Univ. of Kansas, Univ. of Maryland, Univ. of Wisconsin Madison. STATION CONTROLLE R ANTENNA ANTENNA ANTENNA ANTENNA DDA (×4)DATA AND CLOCK DISTRIBUTION SYSTEM SURFACE PROCESS SYSTEM DOWN-HOLE DIGITIZATION SYSTEM PHY RJ45 FPGA Data Cable driver Cable equalizer Clock conditioner Clo ck Standard cat5 cable (250meters) Cable driver FPGA Cable equalizer Clock conditioner 20 MHz clock Cable driver: • Amplifying the incoming clock to transfer it •400 ps rise time, 25 ps output jitter •1 Vpp output •Power consumption: 520 mW Cable equalizer: • equalization • DC restoration •750 mVpp output •Power consumption: 255 mW Clock conditioner: • Loop filtering • Jitter cleaning • Clock distribution •200 fs output jitter •Power consumption: 250 m CAT5 cable Description Mean Std Dev Number of samples Period1, Ch1 50ns 16ps 239988 Period2, Ch2 50ns 27ps 239976 TIE1, Ch1 0s 26ps 240000 TIE2, Ch2 0s 50ps 239988 Skew1, Ch1, Ch2 -8ns 52ps 239988 IP-failure rate (down to -40°C) 1.2E- 8/32bits 4.3E11 (72 hours) Power consumption ~2.3W Precision of period shift between clocks Performance : • Original clock: yellow • Recovered clock: turquoise The challenge : Distance:250 meters Speed: O(10Mbits/s) Time precision : <50 ps Advantages: 4 pairs of differential signals Immunity to common mode noise Standard high speed protocol (10/100/1000Mbps) Disadvantage: Can’t support more than 100 meters (100 Base –T ) Increased signals jitter Standard cat5 twisted pairs FPGA PHY RJ45 Clo ck Data DATA AND CLOCK DISTRIBUTION SYSTEM + With synchronized clock, stable connection can be established between two PHY via 250 meters cat5 cable. PHY 10/100 Mbits/s Ethernet phy, 25MHz input clock In current design: driven by 20MHz clock 8/80 Mbits/s Power consumption: 200 mW clock data Driver and PHY Use different pairs in one cat5 solution Future plan Optical data and clock distribution system (2.5Gbps)
description
An Extended-Range Ethernet and Clock Distribution Circuit for Distributed Sensor Networks Kael Hanson, Thomas Meures, Yifan Yang Interuniversity Insitute for High Energies (IIHE), Brussels. p. The ARA collaboration BELGIUM: Univ . Libre de Bruxelles . GERMANY: Univ. of Bonn, - PowerPoint PPT Presentation
Transcript of An Extended-Range Ethernet and Clock Distribution Circuit for Distributed Sensor Networks
An Extended-Range Ethernet and Clock Distribution Circuit for Distributed Sensor Networks
Kael Hanson, Thomas Meures, Yifan YangInteruniversity Insitute for High Energies (IIHE), Brussels
Motivation : Detecting the GZK-flux
νEM cascade
Radio-Cerenkov cone
37 stationsSpacing: 2 kmDepth under ice surface: 200 mSurface coverage: ~160 km2
Ice thickness below: ~3000 m
Each station:16 + 4 sub-firn antennas (sensitive between 250 and 800 MHz):8 vertically polarized8 horizontally polarized4 calibration pulsers (v-pol + h-pol)X surface antennas
Hpol Quad-slot antennaVSWR < 3 above 300MHz
pARA (THE ASKARYAN RADIO ARRAY )
The GZK-mechanism as a “guaranteed” neutrino source:• Very few protons accelerated to UHE within GZK interaction length (most
accelerators are further away from earth)• →GZK-mechanism should lead to cutoff in the UHECR spectrum• Cutoff confirmed by the Pierre AUGER Observatory
Phys.Lett.B685:239-246, 2010 Detection method:• Emission of coherent radio waves from neutrino-induced EM-cascades
(predicted by Askar’yan, 1962)• Verified at SLAC in 2007
Phys. Rev. Lett. 99, 171101, 2007
Reason:• Radio waves have long attenuation length in ice (~800m), large volumes
with small number of antennas
The ARA collaboration
BELGIUM: Univ. Libre de Bruxelles.
GERMANY:Univ. of Bonn, Univ. of Wuppertal.
JAPAN:Chiba university.
TAIWAN:National Taiwan Univ..
UNITED KINGDOM:Univ. College London.
USA:Ohio State Univ.,Univ. of Delaware,Univ. of Hawaii,Univ. of Kansas,Univ. of Maryland, Univ. of Wisconsin Madison.
STATION CONTROLLER
ANTENNA
ANTENNA
ANTENNA ANTENNADDA(×4)DATA AND CLOCK DISTRIBUTION SYSTEM
SURFACE PROCESS SYSTEM DOWN-HOLE DIGITIZATION SYSTEM
PHY
RJ45
FPGA
Data
Cable driver
Cable equalizer
Clock conditioner
Clock
Standard cat5 cable (250meters)
Cable driver
FPGA
Cable equalizer
Clock conditioner
20 MHz clock
Cable driver:• Amplifying the incoming clock
to transfer it•400 ps rise time, 25 ps output jitter
•1 Vpp output•Power consumption: 520 mW
Cable equalizer:• equalization• DC restoration
•750 mVpp output•Power consumption: 255 mW
Clock conditioner:• Loop filtering• Jitter cleaning• Clock distribution
•200 fs output jitter•Power consumption: 578 mW
250 m CAT5 cable
Description Mean Std Dev Number of samples
Period1, Ch1 50ns 16ps 239988
Period2, Ch2 50ns 27ps 239976
TIE1, Ch1 0s 26ps 240000
TIE2, Ch2 0s 50ps 239988
Skew1, Ch1, Ch2 -8ns 52ps 239988
IP-failure rate (down to -40°C) 1.2E-8/32bits 4.3E11 (72 hours)
Power consumption ~2.3W
Precision of period
shift between clocks
Performance :• Original clock: yellow• Recovered clock: turquoise
The challenge :Distance:250 metersSpeed: O(10Mbits/s)Time precision : <50 ps
Advantages:4 pairs of differential signalsImmunity to common mode noiseStandard high speed protocol (10/100/1000Mbps)
Disadvantage:Can’t support more than 100 meters (100 Base –T )Increased signals jitterStandard cat5 twisted pairs
FPGA
PHY
RJ45
ClockData
DATA AND CLOCK DISTRIBUTION SYSTEM
+
With synchronized clock, stable connection can be established between two PHY via 250 meters cat5 cable.
PHY10/100 Mbits/s Ethernet phy,
25MHz input clockIn current design: driven by 20MHz clock
8/80 Mbits/sPower consumption: 200 mW
clock
data
Driver and PHY Use different pairs in one cat5
solution
Future planOptical data and clock distribution system (2.5Gbps)
