Adaptive CMOS Circuits for 4G Wireless...

11© IMSE-CNM ΣΔ Design Group

Adaptive CMOS Circuits for 4G Adaptive CMOS Circuits for 4G Wireless NetworksWireless Networks

Jose M. de la Rosa and Mohammed Jose M. de la Rosa and Mohammed IsmailIsmail

ECCTD’07 Tutorials, Sevilla, August 30

22© IMSE-CNM ΣΔ Design Group

Adaptive CMOS Circuits for 4G Adaptive CMOS Circuits for 4G Wireless NetworksWireless Networks

Jose M. de la RosaJose M. de la Rosa

[email protected]

ECCTD’07 Tutorials, Sevilla, August 30

Part II: Reconfigurable Data Part II: Reconfigurable Data ConvertersConverters

© IMSE-CNM ΣΔ Design Group


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IntroductionIntroduction

Background on CMOS telecom data convertersBackground on CMOS telecom data converters

Reconfiguration strategiesReconfiguration strategies

Overview of the stateOverview of the state--ofof--thethe--artart

Case studyCase study

ConclusionsConclusions

OUTLINEOUTLINE


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Trend towards wireless telecomEvolution of Cellular (Mobile) Communications

1G: Voice 2G: Voice + SMS (<10kb/s) [GSM]3G: Voice + Broadband Internet Access + Digital Television + …(2Mb/s) [UMTS/WCDMA]4G (Beyond 3G): GSM/UMTS + WPAN/WLAN/WiMAX (+ Bluetooth/UWB…)

Integration of multiple functions into wireless terminalsPhone (voice communication)Data communication (web-browser, e-mail, etc…)Personal Digital AssistanceDigital cameraVideo-game console, etc…

Introduction: Introduction: The Wireless RevolutionThe Wireless Revolution


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New technology scenarios

Software-radio conceptAmbient IntelligentWireless Sensor NetworksImplanted/Wearable systems

CMOS (Deep Sub-micron/Nano) Technology Evolution

Trend to Systems-on-Chip (SoCs) / Systems-in-Package80-90% digital circuitry10-20% analog/RF/mixed-signal circuitry

Nano-scale miniaturization advantages

Higher data-transfer ratiosPortability (lower power consumption)Silicon area reduction (lower cost)Programmability…

Introduction: Introduction: New Technology ScenariosNew Technology Scenarios


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Reconfigurability to different standardsCurrently: separate RF-sections (for each standard) and programmable BasebandPossibility of RF / Baseband reconfiguration ??Study of appropriate transceiver architectures

Implementation of RF/Analog/Mixed-signal circuits in CMOS nanotech.

Switching noiseLow-voltageDeficient modeling, etc…

Portability and low-power consumptionTechnology evolution -> Power supply reduction -> Power consumption increaseSpecially critical for pico-radio applications…

Time-to-market reductionLack of proper CAD tools, specially for RF circuitsLack of systematic (top-down & bottom-up) methodologies for wireless transceivers

Introduction: Introduction: New Technology Scenarios New Technology Scenarios -- IssuesIssues


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Multistandard RF transceivers

Reconfigurable to differentspecifications

Low cost and low power consumption

Data converters

One of the most challenging blocks

Require adaptive specifications

Background on CMOS Telecom Data ConvertersBackground on CMOS Telecom Data ConvertersBackground on CMOS Telecom Data Converters


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ΣΔΣΔ ADCsADCs

NyquistNyquist ADCsADCs

STANDARD BANDWIDTH RESOLUTION

GSM 200 kHz 13-14 bit

UMTS (W-CDMA) 3.84 MHz 9-10 bit

BLUETOOTH 1 MHz 11-12 bit

WLAN (802.11 a/b/g) 20-22 MHz 8-10 bit

WiMAX 20 MHz 8-10 bit

UWB 500 MHz 4-5 bit

GPS 2 MHz 10 bit


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Flash ADCs

Parallel (Fast) A/D conversionExponential increase of • Silicon Area• Power consumption

Limited to 6-8 bitsConversion speed ~ GS/sAppropriate for reconfiguration


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Pipeline ADCs

Stage 1Stage 1 Stage 2Stage 2 Stage kStage kS/HS/H S/HS/HS/HS/H Λ

Digital Correction LogicDigital Correction Logic

N1 N2 Nk

NOut

vo

MDAC

NkDACNk

DACNk

ADCNk

ADC ∑∑ 2Nk2Nk

+

-vi

Nk

Good alternative for medium-high resolution & Video-range conversion rates

Reconfigurability parameters:# of stagesResolution per stageSampling frequency


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SigmaSigma--DeltaDeltaADCADC

NyquistNyquistADCADC

HIGHHIGH--SELECTIVITY ANALOG FILTER SELECTIVITY ANALOG FILTER for antifor anti--aliasingaliasing

Overall resolution obtained using Overall resolution obtained using HIGHHIGH--ACCURACY ANALOG BLOCKSACCURACY ANALOG BLOCKS

LOWLOW--SELECTIVITY ANALOG FILTER SELECTIVITY ANALOG FILTER for antifor anti--aliasing (1st/2nd order)aliasing (1st/2nd order)

High overall resolution obtained using High overall resolution obtained using LOW/MODERATELOW/MODERATE--ACCURACY ANALOG BLOCKSACCURACY ANALOG BLOCKS

HIGHHIGH--SELECTIVITY DIGITAL FILTERSELECTIVITY DIGITAL FILTER

EASIER AND MORE ROBUST IN MODERN CMOSEASIER AND MORE ROBUST IN MODERN CMOS


Sigma-Delta ADCs


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H(z) with large gainwithin the signal band

1st1st--order order ΣΔΣΔMML L thth--order order ΣΔΣΔMM


Sigma-Delta ADCs


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1b 2b 3bΛ

Nb

lsbI lsbI2 lsbI4 lsbN I12 −

ov

Impractical solution because of current glitchesduring on/off switching of the current sources.

☺ Steer current to another low impedance node

Solution

According to the digital input a set of current sources are steerd to a lowimpedance node to get the output voltage

Most suitable solution for high-frequency D/A conversion in wireless telecom

Resolution can be reconfigured by digitally controled switches


Current-Steering DACs


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H(z) with large gainwithin the signal band

L L thth--order order ΣΔΣΔMM

OversamplingOversampling, , OSROSR

Order of the shaping, Order of the shaping, LL

Resolution of the Resolution of the internal internal quantizerquantizer, , BB

Speed of analog circuitry Speed of analog circuitry

Stability of the Stability of the ΣΔΣΔM M

Linearity of the DAC Linearity of the DAC

L B

ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Control parameters : Control parameters : Control parameters


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DT ΣΔM CT ΣΔM

Low-Pass ΣΔM Band-Pass ΣΔM

Nature of the signals being handled: Low-pass vs. Band-pass

Dynamics of the loop filter: Discrete-Time vs. Continuous-Time

Number of bits of the embedded quantizer: single-bit vs. multi-bit

Number of quantizers employed: single-loop, cascade, etc..

Type of primitives available in the fabrication technology…

ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Classification: Classification: Classification


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ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive : Adaptive : Adaptive OversamplingOversamplingOversamplingBasic idea:

To change the effective resolution of the ADC through reconfigurable oversamplingBy changing the sampling frequency (impact on the circuit performance)By changing the signal-bandwidth (not optimum noise-shaping)

Can be combined with the other two strategies, i.e, reconfiguration of L and BUsed in a number of ICs and applications: [Gome02][Salo02][Shim05]…

WCDMA (3.84-MHz)


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ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Loop Filtering: Adaptive Loop Filtering: Adaptive Loop FilteringBasic idea:

To change the effective resolution of the ADC through reconfigurable modulator-loopfilteringMake the order (L) and/or the position of NTF zeros in the signal bandwidthprogrammable

Applied to a number of ΣΔM topologies

Cascade (Low-Pass) ΣΔMs : [Chan04], [Dezz03], [Fara04], [Gero06], [Morg07][Rusu06], [Tiew01], [Zhan04]

Single-loop (Low-Pass) ΣΔMs: [Burg01], [Veld03], [Aria06] [Rusu06b]

Continuous-Time ΣΔMs : [Veld03], [Aria06]

Band-Pass ΣΔMs : [Shoa97], [Card03]

…

0 1 2 3 4 5 6 7 8

x 107

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0Output Spectrum Cascaded 3-2

Mag

nitu

de (d

B)

Frequency (Hz)

L

NTF zeroes


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Systematic loss of resolution, but:

MASH MASH ΣΔΣΔMsMs

Each stage re-modulates a signal containing the quantization error in the previous one.

Digital processing is used to cancel out all quantization errors, but that in the last stage.

Error Cancellation Logic (ECL)Error Cancellation Logic (ECL)

d > 1, interstagecoupling

Smaller than for single loopsIndependent of OSR

HIGHHIGH--ORDER STABLE OPERATIONORDER STABLE OPERATION is ensured by cascading low-order stages (Li = 1, 2).

Relationships among ECL and ΣΔM to be fulfilled for perfect cancellation (NOISE LEAKAGENOISE LEAKAGE).

Performance close to idealPerformance close to ideal

Small spread of analog Small spread of analog coeffscoeffsECL can be easily implementedECL can be easily implemented

Suited at low Suited at low oversamplingoversampling

ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Loop Filtering: Adaptive Loop Filtering: Adaptive Loop FilteringHigh-order Cascade ΣΔ Modulators - Basic Concepts


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ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Loop Filtering: Adaptive Loop Filtering: Adaptive Loop Filtering

22--11LL--22 ΣΔΣΔM M [Mede03][Morg07]

1/4, 1/2, 1/1, 2/1

4L + 1

Minimize the systematic loss of DR

Maximize the overload level

Minimize the integ output swing

Easy implementation of cap ratios

Reduce the number of caps

Power-of-2 digital coeffs (shift registers)

6dB (1bit)

-5dBFS

(0.75, 1, 1, …, 1) xVref

0, 1, 2

Programmable architectureProgrammable architecture

Robust extension to multi-bit

Regardless of the orderRegardless of the order

{L, OSR, B }

2nd-order front-end stageIdentical 1st-order back-end stages

LLthth--order (order (LL--1)1)--stage cascadestage cascade

Expandable Cascade ΣΔ Modulators


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ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Loop Filtering: Adaptive Loop Filtering: Adaptive Loop FilteringReconfigurable Cascade ΣΔ Modulators

Switchable loop-filter coefficients

Single-loop/Cascade reconfiguration

GPRS/WCDMA application [Dezz03]


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GSM

ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Loop Filtering: Adaptive Loop Filtering: Adaptive Loop FilteringReconfigurable Cascade ΣΔ Modulators

Cascade of low-pass and band-pass ΣΔMs: [Tiew01]

Extra feedback paths to make the zeroes of NTF programmable [Zhan04]

WCDMA

WLAN


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OPTIMIZED IIROPTIMIZED IIR NTFNTFss

Complex zeros at |Complex zeros at |z z | = 1 with optimal | = 1 with optimal positions within the signal bandpositions within the signal band

[Schr93]

Butterworth/Butterworth/ChebyshevChebyshev polespoles

(2)(2)

(2)(2)(1)(1)

5th5th--order NTForder NTF((OSR OSR = 64)= 64)

IIRIIR NTFNTFss

Zeros at Zeros at zz = 1= 1

Gain adjusted to satisfy

[Lee87]

Butterworth/Butterworth/ChebyshevChebyshev polespoles

(1)(1)

Programmability of the NTF zeroes – Basic principle



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Ism

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Straightforwardimplementation

Chevychevimplementation



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[Veld03]

NTF zeroes are changed throughthe integrator time-constants

(filter coefficients)



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Ism

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Complex architecture for WLAN (IEEE 802.11 a/b/g)

Suited for ZIF and LIF modes

Gm-C implementation

NTF poles are shifted by usingGM4 and GM5 integrators

Complex loop filter– Example: CT 2x2nd-order 3-bit complex [Aria03]



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ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Loop Filtering: Adaptive Loop Filtering: Adaptive Loop FilteringProgrammability of the notch frequency in BandPass ΣΔMs – Basic concepts


ECC

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TD 2

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ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Loop Filtering: Adaptive Loop Filtering: Adaptive Loop FilteringProgrammability of the notch frequency in BandPass ΣΔMs


ECC

TD 2

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ECC

TD 2

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ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Loop Filtering: Adaptive Loop Filtering: Adaptive Loop FilteringProgrammability of the notch frequency in BandPass ΣΔMs

ResonatorTF

Can be implemented either in SC [Card03]

or CT circuits [Shoa97]


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Element TrimmingElement TrimmingAnalog CalibrationAnalog CalibrationDigital CorrectionDigital Correction

Increased dynamic rangeIncreased dynamic range

Better stability propertiesBetter stability properties

DAC nonDAC non--linearitieslinearities are directly are directly added to the inputadded to the input

B can trade for OSR (wideband)

More aggressive high-order NTFs

The linearity of the ΣΔM will beno better than that

Correcting DAC errorsCorrecting DAC errors

DEM techniquesDEM techniques

DecorrelatingDecorrelating DAC errorsDAC errorsfrom the inputfrom the input

FULLFULL--PARALLEL ADC/DACPARALLEL ADC/DAC(Typically B < 6)

DAC linearity limited byDAC linearity limited bycomponent mismatchcomponent mismatch

Dual quantizationDual quantization

Introducing DAC errorsIntroducing DAC errorsat a nonat a non--critical positioncritical position

POSSIBLE APPROACHESPOSSIBLE APPROACHES

ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Int. Resolution: Adaptive Int. Resolution: Adaptive Int. ResolutionBasic idea: To change the resolution of the internal (flash) quantizer − Concept


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Combines 1-bit and multi-bit quantizers(linearity/reduced error)

Dual QuantizationDual Quantization

LeslieLeslie--SinghSingharchitecturearchitecture

[Lesl90]Concept applied to singleConcept applied to single--loop loop ΣΔΣΔMsMs [Hair91]

Concept applied to cascade Concept applied to cascade ΣΔΣΔMsMs [Bran91]

L-0 cascade ΣΔMSuffers from noise leakageMulti-bit quantization does not improve stability

Improved stabilityNoise leakage

Multi-bit quantization usually applied only in the last stage

DAC errors shaped by L-LNRelaxes DAC requirements

Noise leakage (inherent to cascades)

Basic idea: To change the resolution of the internal (flash) quantizer − Concept

ReconfigReconfig. Strategies . Strategies −− ΣΔΣΔΣΔMsMsMs: Adaptive Int. Resolution: Adaptive Int. Resolution: Adaptive Int. Resolution


ECC

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Target:Target: ~ 14bit @ 4MS/s

Technology:Technology: 0.35-μm digital CMOS3.3-V supplyNo analog capsEpitaxial substrateNovel tech

{ { LL = 4, = 4, OSROSR = 16, = 16, BB = 4}= 4}

ffss = 64MHz= 64MHz

Programmable multiProgrammable multi--bit bit quantization (4, 3, 2 bits) quantization (4, 3, 2 bits)

22--11--1(4b)1(4b)program.program.

Example: A 2-1-1 SC ΣΔM for ADSL+ with programmable multi-bit quant. [Rio06]



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ResistiveResistive--ladder DACladder DAC

The resistor ladder provides the reference voltages to the ADC

30 unit resistors (R = 50Ω) between references of ±1V (2.67mW)

Unsalicided p+ poly used in resistors

Flash ADCFlash ADC

Regenerative latches as comparators

SC scheme for comparing differential input and differential references

Multi-metal caps used (0.25pF)

44--bit bit QuantizerQuantizer


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4bit-to-2bitconversion

4bit-to-3bitconversion

44--bit bit QuantizerQuantizerprogrammable to 2 and 3 bitsprogrammable to 2 and 3 bits


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Reconfigurable Multi-bit + oversampling – Example: A SC 6-bit 2nd-order [Mill03]

Fixed number of bits (B=6) + DEM

Reconfigurable oversampling (by changing both sampling freq. and signal band)

Concept

Block diagram



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Internal quantizer of the ΣΔM implemented as a pipeline ADC [Broo97]

Mainly limited by the mismatch between the analog and the digital part

Applied to Multi-Standard CT ΣΔMs in combination with reconfig. overs. [Giel05]

ReconfigReconfig. Strategies . Strategies −− Hybrid Data ConvertersHybrid Data ConvertersHybrid Data Converters


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ReconfigReconfig. Strategies . Strategies −− Hybrid Data ConvertersHybrid Data ConvertersHybrid Data ConvertersReconfigurable ΣΔ-Pipeline ADCs [Gula01][Basc06]

Take advantage of both data conversion techniques

Use the same building blocks: opamps, comparators, switches, capacitors…

ADC = building blocks + reconfigurable network

[Baschirotto, IEEE CAS Mag. 2006]


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ReconfigReconfig. Strategies . Strategies −− Pipeline ADCsPipeline ADCsPipeline ADCsPipeline ADCs

Less flexible than ΣΔ converters to adapt their performance for MS receivers

Do not use oversampling – More suitable to digitize wider signal bandwidths

Control parameters

Resolution-per-stage

Number of stages

Sampling frequency

Stage 1Stage 1 Stage 2Stage 2 Stage kStage kS/HS/H S/HS/HS/HS/H Λ

Digital Correction LogicDigital Correction Logic

N1 N2 Nk

NOut


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ReconfigReconfig. Strategies . Strategies −− TimeTime--Interleaved Interleaved Pipeline ADCsPipeline ADCsPipeline ADCsTime-Interleaved (BiCMOS) Pipeline ADCs (for BT/WLAN dual-mode DCRs) [Xia06]

Allow to make the overall sampling rate programmable

Sensitive to mismatch among the different ADC branches -> dig. calibration

Application to Bluetooth/WLAN dual-mode Direct-ConversionReceiver


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ReconfigReconfig. Strategies . Strategies −− CyclicCyclic--Pipeline ReconfigurationPipeline ReconfigurationCyclic-Pipeline reconfiguration [Ande05]

Resolution reconfigured by shortening the pipeline

Multiple configurations: 10b@fs, 10b@fs/2, 10b@fs/4, 8b@fs/2, 6b@fs, 6b@fs/2

No variable gain/biasing of amplifiers are used

Extra hardware implemented by digital logic


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ReconfigReconfig. Strategies. Strategies −− CurrentCurrent--Steering Steering DACsDACsFundamentals and reconfiguration parameters

According to the digital input a set of current sources are steerd to a lowimpedance node to get the output voltage

Most suitable solution for high-frequency D/A conversion in wireless telecom

Resolution can be reconfigured by digitally controled switches

1b 2bΛ

Bb

lsbI lsbI2 lsbB I12 −

1t 2tΛ

12 −Tt

lsbB I2 lsb

B I2 lsbB I2

ov

ov


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ReconfigReconfig. Strategies. Strategies −− CurrentCurrent--Steering Steering DACsDACsExample: A 8-bit current-steering DAC for WLAN/UMTS/Bluetooth [Ghit06]

Fixed number of bits (# current sources)

Conversion frequency higher than Nyquist limit

o Increase the effective resolution of the DAC (oversampling)

o Relax post-dac reconstruction filter specifications


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ReconfigReconfig. Strategies . Strategies –– CircuitCircuitCircuit---level techniqueslevel techniqueslevel techniquesCircuit-level reconfiguration techniques

Building-block level:

• Integrator, MDAC, sub-ADC converters, …

• Connect/disconnect circuit elements (capacitors, transconductors, SC branches) to get the required network


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ReconfigReconfig. Strategies . Strategies –– CircuitCircuitCircuit---level techniqueslevel techniqueslevel techniquesCircuit-level reconfiguration techniques

Building-block level:

• Integrator, MDAC, sub-ADC converters, …

• Connect/disconnect circuit elements (capacitors, transconductors, SC branches) to get the required network

Sub-block (transistor, opamp, …) level:

• Biasing reconfiguration to adapt power consumption [Lim06][Ahm06]

• Sizing reconfiguration (parallel connection of basic cells) [Gero06]

• Extra switches: modify the zeroes/poles and increase area

Bacic Cell Control switches


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ReconfigReconfig. Strategies . Strategies –– CircuitCircuitCircuit---level techniqueslevel techniqueslevel techniquesExample: SC integrator with programmable capacitor arrays


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BIAS CURRENT BIAS CURRENT RECONFIGURATIONRECONFIGURATION

ReconfigReconfig. Strategies . Strategies –– CircuitCircuitCircuit---level techniqueslevel techniqueslevel techniquesBias reconfiguration

Most common approach

Allows to adapt the power consumption to the std specs [Ahm06]

Additional current sources activated only when there is slewing [Lim06]


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nGSM nBluetooth nUMTS nWLAN Iref

1 1 2 5 300μA

ReconfigReconfig. Strategies . Strategies –– CircuitCircuitCircuit---level techniqueslevel techniqueslevel techniquesBias reconfiguration: example


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BIAS CURRENT BIAS CURRENT RECONFIGURATIONRECONFIGURATION

TRANSISTOR SIZINGS TRANSISTOR SIZINGS RECONFIGURATIONRECONFIGURATION

ReconfigReconfig. Strategies . Strategies –– CircuitCircuitCircuit---level techniqueslevel techniqueslevel techniquesBias reconfiguration: example


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State of the Art on CMOS MultiState of the Art on CMOS Multi--Standard Data ConvertersStandard Data Converters

Sigma-Delta ADCsAuthor Standard Resolution (bit) BW (Hz) Architecture Process Power (W) Reconfiguration Strategy

WLAN (ZIF mode) 8,7 2,00E+07 CT 2nd-ord 0.25um CMOS 3,04E-02WLAN (LIF mode) 8,6 2,00E+07 3,20E-02 Complex filtering

UMTS 8,4 3,84E+06 1,35E-02GSM 11,7 2,00E+05 1,15E-02

11 2,00E+05 7,50E-03GPRS 13 1,00E+05 2nd-ord Single-loop 0.13um CMOS 2,40E-03UMTS (1.92MHz) 10 1,92E+06 2(5L)-1(5L) 4,30E-03GSM 12,2 2,00E+05 2,40E-03GSM 11,3 2,00E+05 1,40E-03UMTS (2MHz) 7,8 2,00E+06 2,90E-03GSM 10 2,00E+05 1,30E-01CT2+ 10,5 1,00E+05 1,30E-01IS54/AMPS 11,17 3,00E+04 1,30E-01CDMA-2000 11,5 6,15E+05 2,27E-02W-CDMA (1.92MHz) 10,5 1,92E+06 2,27E-02

AMPS 15 1,80E+04 3,00E-02GSM 13,2 2,00E+05 3,00E-02CDMA 12,5 6,25E+05 3,00E-02W-CDMA (1.92MHz) 11,3 1,92E+06 5,00E-02

GSM 11,67 2,70E+05 5,60E-02CDMA 6,68 3,84E+06 5,60E-02GSM 12,66 2,70E+05 BandPass 4th-order Single-loop 0.35um CMOS 2,40E-02IS-95 12,17 1,25E+06 BandPass 4-4 3,70E-02DECT 11,17 1,76E+06 BandPass 4-4 3,70E-02CDMA 7,68 3,84E+06 BandPass 4-0(4B) 3,80E-02

GSM (100kHz) 12,3 1,00E+05 4,00E-03UMTS (2.5MHz) 8,8 2,50E+06 4,00E-03AM 18,5 3,00E+03 5th-order complex CT IF-to-BB 0,18um CMOS 0,21 OVERSAMPLINGFM 1,47E+01 2,00E+05 0,21IBOC 12,7 5,00E+05 0,21GSM 15 2,00E+05 9,10E-03EDGE 14,7 2,71E+05 9,10E-03CDMA 13,5 6,14E+05 1,31E-02UMTS 12 1,92E+06 1,41E-02

[Silv07]

[Shim05]

[Salo03]

[Veld03] BP 5-th order CT (FF) Single-loop 0.18um CMOS

OVERSAMPLING; adaptive filtering

OVERSAMPLING; adaptive filtering

[Aria06]

[Gome02]

Reconfiguration of NTF zeroes; opamp bias adapt

# stages, # bits, loop-filter coefficients,

OVERSAMPLING0.13um CMOS

0.25um CMOS

[Lim06]

[Mill03] 0.18um CMOS

0.13um CMOS2nd-ord Single-loop (11L-DWA)

[Jant97]

[Dezz03]

[Burg01]3rd-ord Single-loop

BandPass 4th-order Single-loop (quadrature/complex) 0.8um CMOS

2nd-ord Single-loop (5L-ILA)

0.18um CMOS OVERSAMPLING3rd-order Mixed-Mode integrators

OVERSAMPLING

OVERSAMPLING

OVERSAMPLING

2nd-ord Single-loop (6B-DWA)

Single-loop/Cascade

[Salo02]BandPass 4th-order Single-loop

0.35um CMOS OVERSAMPLING


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Sigma-Delta ADCs ~ 70%

ΣΔ-Pipeline ADCs ~ 10%

Pipeline ADCs ~ 15%

DACs ~ 5%

SigmaDelta-Pipeline ADCsAuthor Mode Standard Resolution (bit) BW (Hz) Architecture Technology Power (W)

15,39 9,77E+03 1,77E-0214,8 9,77E+03 9,42E-0314,21 9,77E+03 4,26E-0313,33 9,77E+03 2,15E-0312,46 9,77E+03 1,85E-0311,38 9,77E+03 1,70E-03

9,7 9,77E+03 1,58E-0311 2,46E-026

Sigma-Delta GSM (100kHz) 10,89 1,00E+05 2nd-order Single-loop 5,50E-03Pipeline UMTS (3MHz) 4,76 3,00E+06 4 Stage (2b) 5,50E-03

[Gula01]

[Yurt04] 0.25 um CMOS

Sigma-Delta

4th-order Single-loop (FeedForward)

16-stage

0.6um CMOS

Pipeline

Pipeline ADCsAuthor Standard Resolution (bit) BW (Hz) Architecture Technology Power (W) Reconfiguration Strategy

8,9 5,00E+02 1,50E-05 Bias current reconf.N/A 8,9 2,50E+07 3,50E-02N/A 9,5 5,00E+06 8,10E-02 Cyclic-Pipeline

9,1 4,00E+07 9,40E-02WLAN 9,1 1,00E+07 9,80E-03 # stages

5,1 1,00E+07 3,50E-03

[Ahme05] 0,18um CMOS9 ST (1.5B)

[Audo06] 0.18um CMOS

8 ST (1.5B) + 2B 0.18um CMOS [Ande05]

Other data converters being explored in adaptive wireless systems:

Example: A SAR 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Networks [N. Verma and A. Chandrakasan, JSSC, June 2007]


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0

2

4

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8

10

12

14

16

18

20

1,E+03 1,E+04 1,E+05 1,E+06 1,E+07 1,E+08

Signal Bandwidth (Hz)

Effe

ctiv

e R

esol

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n (b

its)

Sigma-Delta

SigmaDelta-Pipeline

Pipeline


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Case Study: Case Study: System planning and ADC specificationsSystem planning and ADC specificationsSystem planning and ADC specificationsRF Receiver RF Receiver

SpecificationsSpecifications

Behavioral Behavioral

SimulationSimulationOptimizerOptimizer

HighHigh--level Sizinglevel Sizing

Layout & EM VerificationLayout & EM Verification

Electrical Electrical

SimulationSimulationOptimizerOptimizer

Cell SizingCell Sizing

VerificationVerification

BER, PER NF, IIP3, IIP2,…

Building- Block specifications:- Gain, NF, Distortion- …ADC Specifications- Effective resolution- Bandwidth


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Behavioral models of the building blocks in MATLAB/SIMULINK including:

• Bandwidth• Amplification• Noise figure (NF)• Non-linearity (IIP2, IIP3)

Verification of the receiver specs for each standard• Noise figure• Intercept points• Level diagrams

Can be combined with optimization for high-level synthesis

Case Study: Case Study: System planning and ADC specificationsSystem planning and ADC specificationsSystem planning and ADC specifications


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Standard specifications

Building block specifications



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Getting the ADC specs for Getting the ADC specs for each standard each standard


Case StudyCase Study


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Case Study: Case Study: ADC architecture selectionADC architecture selectionADC architecture selection

Restricts values of OSRBW,UMTS expands to 4MHz

Easy frequency division from a Easy frequency division from a master clockmaster clock

fs = fclk ÷ {1, 2, 4, …} with fclk= 80MHz max.

Vref = 1.2V to maximize SNDR peak

MultiMulti--standardstandardΣΔΣΔ modulatormodulator

{L, OSR, B} candidates with minimum power

consumption

GLOBAL CONSTRAINTSGLOBAL CONSTRAINTS

Modulator reference fixed according to signal Modulator reference fixed according to signal power at ADC inputpower at ADC input

Cap matching issuesCap matching issues

Minimum unit cap, Cu,min = 0.25pFSampling capacitor, Cs = n × Cu


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22--11LL--22 ΣΔΣΔM M [Mede03][Morg07]

1/4, 1/2, 1/1, 2/1

4L + 1

Minimize the systematic loss of DR

Maximize the overload level

Minimize the integ output swing

Easy implementation of cap ratios

Reduce the number of caps

Power-of-2 digital coeffs (shift registers)

6dB (1bit)

-5dBFS

(0.75, 1, 1, …, 1) xVref

0, 1, 2

Programmable architectureProgrammable architecture

Robust extension to multi-bit

Only the last stage is multi-bit(L-1)th-order shaping for multi-bit DAC errorsAvoids correction/calibration

Dual quantizationDual quantization

Regardless of the orderRegardless of the order

{L, OSR, B }

2nd-order front-end stageIdentical 1st-order back-end stages

LLthth--order (order (LL--1)1)--stage cascadestage cascade

Candidate architecture: Expandable Cascade Candidate architecture: Expandable Cascade ΣΔΣΔMM


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HighHigh--level estimation of power consumptionlevel estimation of power consumption

Quantization errorQuantization error(last stage)(last stage)

Shaped errorsShaped errors = f (Vref , {L, OSR, B }) + f (Vref , OSR, ADC , σC ) + f (Vref , L, OSR, INLDAC)

Thermal noiseThermal noise = f (CS , OSR )

Settling errorSettling error = f (CS , parasitics, GB, SR, OSR, Vref )

Resolution = f ({L, OSR, B }, Vref , σC , INLDAC , ADC , CS , GB, SR )

For given Vsupply , {L, B, OSR }, and σC …

and assuming certain ADC and INLDAC …

the value of CS for obtaining a given DR can be estimated.

CS (and some parasitics) fixes the integrator equivalent load …

and the required amplifier dynamics can be obtained.

The amplifier topology sets the approximated current absorption.

MultiMulti--bit DAC errorbit DAC errorDominant noise leakagesDominant noise leakages(DC gain, cap mismatch)(DC gain, cap mismatch)

ProcedureProcedure::



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Ranking of cascade Ranking of cascade ΣΔΣΔM candidates according to power estimationsM candidates according to power estimations


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Ranking of cascade candidates according to power estimations Ranking of cascade candidates according to power estimations (cont.) (cont.)


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SingleSingle--bit or multibit or multi--bit quantization bit quantization (2, 3, or 4 bits)(2, 3, or 4 bits)

GSMGSM

{4, 1, 50}{3, 2, 50}{3, 1, 100}

BluetoothBluetooth

{4, 1, 20}{3, 3, 20}

UMTSUMTS

{3, 4, 10}{4, 2, 10}

REQUIREMENTSREQUIREMENTS

3rd3rd-- and 4th order cascadesand 4th order cascades

Sampling frequency = 20, 40 or 80MHzSampling frequency = 20, 40 or 80MHz

Sampling cap = 0.25pF, 0.5pFSampling cap = 0.25pF, 0.5pF

Final choice for each standard based on:

More accurate More accurate behavioral behavioral simulationssimulations

BuildingBuilding--block block requirementsrequirements


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Refined buildingRefined building--block requirementsblock requirementsSIMSIDESSIMSIDES, SIMulink-base time-domain SIgma-DEltaSimulator [TCAS-I, 2005]

Validate the DR of the selected ΣΔMs (quantization noise + kT/C noise)Determine max. input noise for each amplifierDetermine the required amplifier dynamics (GB, SR)Refine DC gain and SR at the front-end integrator



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Fine tuningFine tuning


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Fine tuningFine tuning

Selected reconfiguration modesSelected reconfiguration modes

• GSM: L=3, B=1, OSR=100

• Bluetooth: L=4, B=1, OSR=20

• UMTS: L=4, B=2, OSR=10


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Case Study: Case Study: Selected architectureSelected architectureSelected architecture

Architectural/circuital Architectural/circuital reconfiguration: reconfiguration: 2 control signals:

2 of master clock (80MHz)

Bias currents adaptation

Last-stage power down

Resolution at the last stage

(1bit / 2bit)

Variation of the last-stage

integration capacitor

(0.25pF / 0.5pF)

Expandable Cascade SC Expandable Cascade SC ΣΔΣΔMM


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gm

Ci

VER

IFIC

ATI

ON

VER

IFIC

ATI

ON

Architecture

Resolution

Vref

Ron

io

SC, SI, CT

Quantizer

Av

Design SpaceExploration

Modulator Specs.Circuit Technique

Electrical Simulator

Advanced Optimizer

CELL SIZING

Performanceevaluator

Advanced Optimizer

HIGH-LEVEL SIZING

LAYOUT

…

…

…

Case Study: Case Study: HighHighHigh---level Sizinglevel Sizinglevel Sizing

Behavioral SimulatorBehavioral SimulatorSIMSIDESSIMSIDES

[TCAS[TCAS--I, Sept. 05]I, Sept. 05]

Hybrid OptimizerHybrid OptimizerFRIDGEFRIDGE

[JSSC, July 95][JSSC, July 95][Springer, 2006][Springer, 2006]


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Case Study: Case Study: BuildingBuildingBuilding---block specificationsblock specificationsblock specifications


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Case Study: Case Study: Design of building blocksDesign of building blocksDesign of building blocks

Folded-cascode amplifiers:

Basic transistor sizing is the same one

Larger differential pair in 2nd and 3rd integs.

Comparators: pre-amplif. stage + regen. latches

MiM capacitors and standard CMOS switches

2-bit converter: resistive DAC + flash ADC

On-chip auxiliary blocks:

Reference voltage generator

Currents generator

Clock phases generator

Illustrating Bias Current Reconf.


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Case Study: Case Study: Layout issuesLayout issuesLayout issues

Dedicated analog, mixed, and digital supplies

Layout symmetry and common-centroid techniques

Guard rings with dedicated pad/pinIncreased distance among analog and digital blocks

Shielded bus for distributing the clock signals Extensive on-chip decoupling Pad ring divided blocking cells Multiple bonding techniques


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Case Study: Case Study: Simulation resultsSimulation resultsSimulation results

GSMGSM BluetoothBluetooth

UMTSUMTS


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Case Study: Case Study: Simulation resultsSimulation resultsSimulation results


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Case Study: Case Study: Test, PCB and prototypingTest, PCB and prototypingTest, PCB and prototyping

SDMS-ASIC

Title

Size Document Number Rev

Date: Sheet of1 1

Insti tuto de Microelectrónica de Sevilla

Abril, 2007

1.0

PLACA DE UBICACION DEL ASIC SIGMA DELTA MULTIESTANDAR

R2

600k

U1ASIC SDMS

fsel1CLK 2

VD

DDD

123

VS

SDD

124

VDD

IO33

5VS

SIO

336

Y3b0 7Y3b18

Y1 9Y210Y3 11V

DD

IO33

13V

SS

IO33

14

GSM_bias15

EXT_RES16

VSS

AA17

VDD

AA

18

VSS

AA

19V

DDA

A20

VS

SG

AA

21

SB_bias22

SB24

IN-25

IN+26

GSM27

REF-28

REF+29

PD30

CM31

VSS

ADm

ix37

VS

SGA

D41

VSS

DD3

342

VS

SGD

D33

44V

DD

DD

3343

VD

DAD

buff

40V

SS

ADbu

ff39

VDD

AD

mix

38

NC12

NC 23

NC32

NC 33

NC34

NC35

NC 36

CONN4 CONN_PENT_DOWN

AR7

AR

7

AU

7AU

7

AR9

AR

9

AU

9AU

9

AR

11A

R11

AU

11AU

11

AR13

AR

13

AU

13A

U13

AR15

AR

15

AU

15AU

15

AR

17A

R17

AU

17AU

17

AR19

AR

19

AU

19A

U19

AR21

AR

21

AU

21AU

21

AR

23A

R23

AU

23AU

23

AR25

AR

25

AU

25A

U25

AR27

AR

27

AU

27AU

27

AR29

AR

29

AU

29AU

29

AR31

AR

31

AU

31A

U31

VDD

AD

mix

VD

DDD

33

VDD

IO33

VDD

AA

VD

DA

Dbu

ff

VD

DD

D12

CONN3

CONN_PENT_LEFT

C1C1

C3C3

E1 E1

E3E3

G1G1

G3 G3

J1J1

J3J3

L1L1

L3L3

N1N1

N3 N3

R1 R1

R3R3

U1U1

U3 U3

W1W1

W3W3

AA1 AA1

AA3AA3

AC1AC1

AC3 AC3

AE1AE1

AE3AE3

AG1 AG1

AG3AG3

A3 A3

AJ1AJ1

AJ3 AJ3

AL1AL1

AL3AL3

AN1AN1

AN3AN3

AR1AR1

AR3AR3

AU1 AU1

AU3AU3

VDD

IO33

CONN2

CONN_PENT_RIGHT

C35C35

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Low-distortionsignal generator

Digital test unit

WorkstationWorkstation

PCBPCB clocksupply, reference

input bit streams

bit streamsTest SetTest Set--UpUp Cancellation logic

64k-sample FFT

Chip & PCBChip & PCB



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Case Study: Case Study: Experimental resultsExperimental resultsExperimental results

UMTSUMTS

GSMGSM BTBT


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Case Study: Case Study: Performance SummaryPerformance SummaryPerformance Summary


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MultiMulti--Standard chipsets are needed for 4G wireless handheld devicesStandard chipsets are needed for 4G wireless handheld devices

Data converters are key elements for system adaptabilityData converters are key elements for system adaptability

Suitable architectures to be implemented in nanometer CMOS:Suitable architectures to be implemented in nanometer CMOS:

Flash, Pipeline, Flash, Pipeline, ΣΔΣΔ ADCsADCs

CurrentCurrent--steering steering DACsDACs

Combination of the above techniquesCombination of the above techniques

Reconfiguration strategies must combine architecturalReconfiguration strategies must combine architectural--level and level and

circuitcircuit--level strategies to adapt the performance of the required level strategies to adapt the performance of the required

transceivers with optimized power dissipation.transceivers with optimized power dissipation.

CONCLUSIONS CONCLUSIONS


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ReferencesReferences[Ahme05] I. Ahmed and D.A. Johns: “A 50-MS/s (35mW) to 1-kS/s (15μW) Power Scaleable 10-bit Pipelined ADC Using

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[Burg01] T. Burger et al.: “A 13.5-mW 185-Msample/s ΔΣ Modulator for UMTS/GSM Dual-Standard IF Reception.”IEEE Journal of Solid-State Circuits , Vol. 36, pp. 1868-1878, Dec. 2001.

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Sampling ΣΔ Modulator and a Flash Converter." IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 53, pp. 2109-2124, Oct. 2006.

[Ghit06] N. Ghittori et al. : “1.2-V Low-Power Multi-mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters.” IEEE Journal of Solid-State Circuits , Vol. 41, pp. 1970-1982, Sept. 2006.

[Giel05] G. Gielen and E. Goris: “Reconfigurable front-end architectures and A/D converters for flexible wirelesstransceivers for 4G radios.” Proc. of the IEEE Emerging Technologies Workshop (ETW), 2005.

[Gome02] G. Gomez and B. Haroun: “A 1.5V 2.4/2.9mW 79/50dB DR ΣΔ Modulator for GSM/WCDMA in 0.13μm Digital Process.” Proc. of the IEEE Int. Solid-State Circuits Conf. (ISSCC), 2002.

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Acknowledgments Acknowledgments

This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC and the Spanish Ministry of Industry, Tourism and Commerce (FIT-330100-2006-134 SPIRIT).

Some materials have been adapted from presentations by Dr. Rocío del Río and Mr. Alonso Morgado, IMSE-CNM (CSIC/University of Seville).

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