A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning … · February 13th 2007 ISSCC'2007 Session 9...

ISSCC'2007 Session 9 Paper 1

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS ADPLL in 65nm SOI

A. V. Rylyakov1, J. A. Tierno1,G. J. English2, D. J. Friedman1,M. Meghelli3

1IBM T.J. Watson Research Center, Yorktown Heights, NY2IBM Systems and Technology Group, Poughkeepsie, NY3IBM Systems and Technology Group, Hopewell Junction, NY

February 13th 2007 ISSCC'2007 Session 9 Paper 1 1

PLL for Microprocessors and ASICs

Low period jitter needed to increase usable cycle timeLots of programmability needed for ASIC applicationsADPLL performance should track other digital circuits over manufacturing corners


All Digital PLL (ADPLL) Architecture

DCOBB

PFD

DigitalPIDFilter

Σ∆

ClockDivider

EarlyLate

C1

Divide-by-N ClockDivide-by-M Gate

SCLKData In

Data Out

3 3MSB

LSB

Vdda

DCCBuffer

Serial Interface Control and Registers

Ref Clock ClockOut


Self-timed Bang-bang PFD

Ref Clk

Mutex

C

Asynchronous Reset

C-element

Mutex

C

Ref Leads (Late)

Div Leads (Early)

A

B

A First

B First

Div Clk


Mutual-exclusion Element (Mutex)

A

B

B FirstMutex detects which of A or B makes a high-to-low transition first.It is reset by A and B going high

These nodes may go metastable

Au

BuAFirst and BFirst are not resolved until Au and Bu differ by at least Vth

Metastability filter

A First


PID Loop Filter Architecture

5

5

Early/Late

Overflow

Underflow

+Prop+Prop+Diff-Prop-Diff

-Prop

1

0

11

10

01

00

2

5

5

5

5

5-bit arithmetic combines with the DCO control to implement 14-bit arithmetic

Prop = Proportional constantDiff = Differential constantInt = Integral constant

OverflowPUnderflowP

FractionalFrequency

+Int-Int


3rd Order MASH Σ∆

5

5 Cy 1

5

5

Cy 3

5

5 Cy 3

Cy 2

Cy 2

Cy 1

ToDitheredControl

FractionalFrequency

From Loop Filter


DCO Inverter Array and Control

Inverter Array

012

…

…

……

…

From Sigma Delta / Loop Filter

Row Override 012 012

012 012012 012012 012

012012012

012 012 012

271 Inverters per phase

Phase0

Phase1

Phase2

Dither Control

Row

Control

Column ControlFrom Loop Filter

ShiftControl


DCO ControlLoop Filter Underflow/Overflow

…

Shift by -1, 0, 1

csel0

csel1

csel2 …

Shift by -1, 0, 1

rsel0

rsel1

rsel2

Column Underflow / Overflow

‘0’

‘1’

…

Row Even/Odd/First/LastColumn Control Row Control


DCO Array

0 1 2

20 1

2

Some inverters are turned off

Phase 0Phase 1

0 1 Phase 2

2

Output frequency a function of “filling factor”: fraction of tri-state inverters turned on

Some inverters are turned on

0 1

20 1


Single Tri-state Inverter with Control

Phase (i mod 3)

rsel j+1rsel j

csel i (j even)Not csel i (j odd)

Also performs conversionfrom VDD to VDDA

VDDA

Phase ((i+1) mod 3)


Design for Manufacturing Test

All digital logic is connected to a scan chain, and is LSSD testable (Level Sensitive Scan Design)The only “analog” component, the ring oscillator, can be tested this way as well Checking for locking range can be executed digitally


ADPLL Floorplan, 65 nm SOI

Σ∆LoopFilter

RowControl

Clock

Divider

PFDPhold

Row/ColControl

200 µm150 µm

DCO

ColumnControl


Design Summary

200 µm × 150 µm, generously floor-planned layout

Area

Self-timed, bang-bang PFDPFD

Digital PID filter running at divided frequency. 1 MHz to 20 MHz programmable loop bandwidthThird order MASH Sigma Delta

Loop filter

Three stage ring oscillator. Tri-state inverters switched on-off to change gm of the ring stages. 800 frequency steps

DCO (Digitally Controlled Oscillator)

All static standard cell CMOS in 65nm SOI, 2 versions (HVT, RVT FETs). Custom design for tri-state inverter and metastability filter

Implementation


VHDL SimulationsFrequency / Phase acquisition

Pink -> reference cycle timeWhite -> output clock cycle time

Zero-crossing data is passed to Matlab for spectral processing


Simulated Phase Noise Plot


Closed Loop Phase Noise, 4 GHz, 1.2V, 100ºC

1st Order Σ∆2nd Order Σ∆

0th Order Σ∆

2nd Order Σ∆ 1st Order Σ∆ 0th Order Σ∆


Period Jitter, 4GHz Output, 0.5 GHz Ref., 1.2V Supply, 100ºC, 2nd Order Σ∆

0.7 psStd Dev

254 psMax Tcycle

246 psMin Tcycle

250 psMean Tcycle

T1 T2 T3 T4 … Ti

In general, T1≠T2≠… Figure is histogram of measured Ti’s


Period Jitter, 1GHz Output, 125 MHz Reference, 0.5V Supply, 100ºC, No Σ∆

3.0 psStd Dev

1012 psMax Tcycle

987 psMin Tcycle

1000 psMean Tcycle

T1 T2 T3 T4 … Ti

Power dissipation: 1.6 mWPower dissipation: 1.6 mW


N-Cycle Jitter Accumulation, 1.2V, 100ºC, 4GHz, 2nd Order Σ∆

0

4

8

12

16

20

0 1 2 3 4 5 6 7 8 9 10log2 N

Acc

umul

ated

Jitt

er (R

MS

, ps)

125MHz250MHz500MHz

Reference Frequency


DCO Tuning Curves, 100ºC

0123456789

0 0.2 0.4 0.6 0.8 1DCO Fill Factor

Osc

illat

ion

Freq

uenc

y (G

Hz)

0.3V 100C HVT0.5V 100C HVT0.7V 100C HVT0.9V 100C HVT1.1V 100C HVT1.3V 100C HVT1.3V 25C RVT


Test Results

0.5 V -> phase lock up to 1 GHz1.3 V -> phase lock up to 8 GHz (RVT)

Power Supply range

-110 dBc/Hz @ 10 MHz, 500 MHz reference, 4 GHz output, 2nd order Σ∆

Phase Noise

Period: 0.7 ps Long term: 5 psCycle to cycle: 1.1 ps

Jitter (RMS)

1.6 mW / GHz @ 0.5V8 mW / GHz @ 1.2V

Power

400 MHz to 8 GHz measuredLocking range


ConclusionWe designed, simulated and tested an ADPLL in 65 nm SOIThe ADPLL is ideally suited for µP and ASIC applications in advanced CMOS technologyAll static CMOS implementation allows this circuit to work over a wide voltage range (0.5V to 1.3V)

Useful for very low power circuits (1.6 mW @ 1 GHz)Allows for VDD regulation (e.g. from 1.2V down to 0.6V) while still maintaining ASIC level performance

Digital design = Scalable, testable, predictable

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning … · February 13th 2007 ISSCC'2007 Session 9...

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