A Folded, Low-Power Ultra-Wideband CMOS Power … inductance between inductor L 1 and L 2....
Transcript of A Folded, Low-Power Ultra-Wideband CMOS Power … inductance between inductor L 1 and L 2....
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Abstract— A self-biased folded CMOS power detector with
input matched to 50 Ω is proposed and demonstrated in this
paper. The self-biased folded power detector utilizes the short-
channel MOS transistors’ nonlinearity characteristic in
saturation and subthreshold regimes to obtain the power
information of the input RF signal, and the transistors’ operation
regime depends on input power levels. A quasi T-coil matching
network providing matching over 20 GHz operation frequency
range is designed and added. An embedded amplifier is added to
improve the power detector sensitivity at low level power input.
The circuit fabricated in 0.13 μm CMOS process occupies an
active area of 0.085 mm2. In the 0.5 GHz -20 GHz frequency
range, the measured results show that the input dynamic range is
up to 47 dB and the sensitivity is 26.8 mV/dB. The output
response is nearly frequency independent, varying by less than
1.9 dB for a given input power level as the frequency is swept
across the linear operation range. With a standard 1.2-V supply
voltage, the static power consumption is 0.1 mW and it decreases
to 2×10-4 mW with a 0.5 V supply. The performance of the power
detector does not deteriorate with lower supply voltages.
Index Terms— CMOS, large dynamic range, low power, low
voltage, nonlinearity, power detectors, ultra-wideband.
I. INTRODUCTION
IGNAL power detectors (PD) are widely used in wireless
communication systems, which often use automatic-gain-
control (AGC) circuits to minimize power consumption and
optimize system performance [1]-[2]. The activation of AGCs
is determined by the received or transmitted signal levels
obtained from PDs. Power detection is also essential in the six-
port system shown in Fig 1, which has been developed for
reflectometer [3]-[4] and communication receiver [5]-[6]
applications. For the six-port measurement system, when a
load (i.e. device under test, DUT) is connected to port 2, its
complex reflection coefficient can be determined by the power
readings measured at ports 3-6. The received signal is
connected to port 2 in communication receivers and the
Manuscript received October 9, 2009. This work is supported by NSF
#ECCS-0703042.
Chaojiang Li, Pingshan Wang, are with the department of Electrical and
Computer Engineering, Clemson University, Clemson, SC 29634 USA (e-
mail: chaojil, [email protected]).
Fei Gong, Joanne DeGroat are with the Electrical Engineering Department,
the Ohio State University, Columbus, OH 43210 USA (e-mail: gongf,
modulation states of the received signal are detected by the
power information from ports 3-6. Many of these PD
applications require wideband operations, e.g. PDs for ultra-
wide-band (UWB, 3.1GHz - 10.6 GHz) applications.
Fig. 1. Schematic of a six-port for communication or measurement system.
There are several methods for implementing on-chip PDs,
such as diode detectors, Joules-heating-based detectors which
require special attention to packaging, bipolar and CMOS
detectors. Though Schottky diode detectors are good
candidates for RF signal detection, Schottky diode are not
standard components in the CMOS foundry processes and
their performance depends on the process technologies
provided by the foundries [7]. Many efforts are also underway
to develop bipolar transistor (BJT) power detectors [8]-[9].
However, these are incompatible with the CMOS processes
frequently used to fabricate other system parts. Though a
MOSFET power detector operating in deep triode has been
demonstrated [10], the use of the resonant cavity limits the
techniques to narrowband and makes it not amenable to
integration. Using the square-law nature of CMOS transistor
ID-VGS characteristics to obtain input power information, the
power detector in [11] achieved a 20 dB input dynamic range
with multiple off-chip matching networks from 0.125 GHz to
8.5 GHz. Recently, using NMOS devices in the triode regime,
an average current proportional to RF input power was
generated [12]. The current was then converted to voltage and
was amplified with a piecewise linear logarithmic amplifier.
The PD achieved an operating range from 3.1GHz to 10.6
GHz with a ~35 dB input dynamic range. The maximum
detectable input power was ~ -10 dBm.
Most recent researches on power detectors have emphasized
AGC applications which require low level power detection and
low power consumption. However, for the six-port system in
A Folded, Low-Power Ultra-Wideband CMOS
Power Detector with an Embedded Amplifier
Chaojiang Li, Student Member, IEEE, Fei Gong, Student Member, IEEE, Joanne DeGroat, Member,
IEEE, Pingshan Wang, Member, IEEE
S
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Fig. 1, the power level in each port varies significantly with the
input signal in port 2 which is connected to either a DUT in
the measurement system or the received signal in a
communication receiver. Therefore, the PDs require much
larger input dynamic ranges compared with those reported PDs
in [10]-[12]. Furthermore, input matching is vital for the six-
port systems to avoid performance degradation [3]-[6]. Even
in circuits without matching requirements, the PDs input
matching networks can flatten the ratio of input power/source
power versus frequency, as the input reflection coefficient
varies due to frequency changes under non-matched condition.
However, on-chip broadband matching has not been used in
power detectors for these existing structures. In this work, we
demonstrate, for the first time, an on chip quasi T-coil
matching circuit which provides input matches from 0.5 GHz
to 20.5 GHz and a self-biased folded power detector with an
embedded amplifier. The transistors in the self-biased folded
structure operate in saturation or subthreshold regime
depending upon the input power levels. Thus, the input
dynamic range is expanded. The embedded amplifier enhances
the sensitivity of the power detector at low level input power
while the folded PD reuses biasing currents to minimize the
power consumption. This paper is arranged as follows.
Section II describes the analysis of a new wideband matching
network. Section III details the operating principle of the
MOSFET transistor detectors. Section IV presents
measurement results and Section V concludes the paper.
II. WIDEBAND MATCHING CIRCUIT
A T-coil structure, shown in Fig 2(a) [13]-[15], is a
possible choice for broadband matching. Here, K’ is the
mutual inductance between inductor L1 and L2. Unfortunately,
the T-coil is not a standard CMOS component in commercial
foundry processes. Moreover, controlling T-coil performance
is difficult due to different parameters in different foundry
processes and process variation. Furthermore, the following
relationship is required for broadband T-coil matching:
216
LB
CC
(1)
where ζ is the damping factor of the network transfer function
and CL is the load capacitance [13]. Part of CB is from the
parasitic capacitance, Cp (not shown), between the two
terminals of the transformer. This structure fails when load
capacitance CL is much smaller than the parasitic capacitance
Cp. To save power consumption in the PD design, the parasitic
capacitance of the transistor which is the load of the matching
network is usually very small, so the T-coil cannot be used
here. To solve this problem, we propose a quasi T-coil
matching circuit, shown in Fig 2(b).
To match the self-biased folded power detector, which will
be discussed in Section III, two loads Zload1 and Zload2 are
added suppositively in Fig 2(b). The matching circuit can be
treated as a three-port network, one input port and two output
ports; the input port is connected to the signal source, and the
two output ports are connected to Zload1 and Zload2 respectively.
In other applications with a single load, the load can be added
to either position of Zload1 or Zload2. To determine the
component values in the proposed quasi T-coil circuit, a
unified case is considered in the following analysis. If we
assume the source voltage is Vs and resistance is Z0 as shown
in Fig 2(a), then the voltage transfer coefficients for Zload1 and
Zload2 in Fig 2(b) are
2 01 2
2 0
1 1 inload in
in
Z ZT
Z Z
. (2)
22 1
2
3
3 2
1 2( 2 )
1 1 1( 2 )( )
R PL
load load
R PL
sC sC sC sCR sL
T T
sC sC sC sC sC sCR R sL
, (3)
(a)
(b)
Fig. 2. (a) T-coil network. (b) Proposed quasi T-coil circuit. CPL and CR are
the parasitic capacitors of L and R2 respectively.
When input Zin2 is matched to Z0, the reflection coefficient
Γin2 ≈ 0 and the voltage transfer coefficient for Zload1 is Tload1 ≈
1 which should be valid in the matching frequency range. The
relationship of R2 with the load resistor R1 and R3 can be
obtained via condition Re (Zin2) ≈ Z0
0 12
1 0
Z RR
R Z
(4)
in which R1 > Z0 is required. From Im(Zin2) ≈ 0 in the matching
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frequency range, the inductance L can be expressed as follows:
0 2 1 1
0 3 2 1 3 1 2 3 31 0
( 2 )1
( )( 2 ) ( 2 )
RZ R R C C CL
Z R R R C C R R R C CR Z
. (5)
The DC output of the PD is related to the amplitude of the
input RF signals as the discussion in Section III, the voltage
transfer ability is important to the sensitivity of the PD. To
guarantee a reasonable voltage transfer to Zload2, at the
designed center frequency, C should satisfy
2
2
3
3 2
1 2( 2 )
1
1 1 1 2( 2 )( )
R PL
R PL
sC sC sC sCR sL
sC sC sC sC sC sCR R sL
. (6)
Thus, all the parameters in the quasi T-coil structure in Fig
2(b) are determined.
To match the folded power detector discussed in Section III,
the following parameters are chosen: R1 = R2 = R3 = 104 Ω, L =
0.894 nH, CPL = 0.7 pF, C= 60 fF, C1 = 1 fF, C3 = 7.5 fF, CR =
0.16 fF. The simulation results of the voltage transfer function
for Zload2, Vout/Vin versus frequency using MATLAB is given in
Fig 3. At 10 GHz, | Vout/Vin | approximates to 0.5.
Fig. 3. Simulated voltage transfer function for Zload2 in Fig 2(b).
As shown in Fig 3 the voltage transfer property for Zload2 is
poor at the low frequencies (i.e.500 MHz), due to the large
impedance caused by C. It is also opposite to that of the T-coil
matching structure in Fig 2(a), which exhibits poor voltage
transfer characteristics at high frequency ranges.
III. POWER DETECTOR DESIGN
Fig. 4 shows two folded power detectors configured for RF
power detection. The shared drains of M1 and M3, and of M2
and M4 are the AC ground. Fig 4(a) is a folded power detector
matched with resistors. Fig 4(b) is our proposed self-biased
folded power detector matched with the quasi T-coil network.
An amplifier comprising M2 and M4 is embedded to enhance
the sensitivity of the power detector at low level input power
without increasing the power consumption, compared to Fig
4(a). The amplifier also simultaneously decreases the DC
power consumption. When there are no RF signals, M1, M2,
M3, and M4 all operate in the saturation regime and the output
voltage (Vout+-Vout-) is zero if the secondary effects are ignored
since the PD is symmetric in DC operation. For very low level
input power, Vout- shows a small decrease. Though difficult to
detect directly, the embedded amplifier boosts the output
voltage (Vout+ -Vout). As the input power level further increases,
Vout- will decrease significantly and Vout+ will increase or even
reach Vdd. M1 and M2 will enter the subthreshold regime when
Vout- < Vth, where Vth is the threshold voltage of the transistors.
Thus, the power detector can operate at very low and very high
levels of input power. In those structures, the DC currents
through the transistors are very small. Particularly, when
transistors operate in the subthreshold regime, the DC power
consumption decreases dramatically compared with the power
consumption in Fig 4(a).
(a)
(b)
Fig. 4. (a) A folded power detector matched with resistors and (b) the
proposed self-biased folded power detector with quasi T-coil matching
network and an embedded amplifier.
The principle of operation for CMOS power detectors has
been discussed in [11] with long channel transistor model, but
the results cannot describe the relationship between the
sensitivity and the DC bias voltage. Since the transistors in the
proposed structure may operate in saturation or subthreshold
regimes at different input power levels, a unified equation to
describe the principle of operation and sensitivity of the PD is
necessary. For a general two-port system, one can write a
Taylor series expansion relating input and output variables, i.e.
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the drain current of a short-channel MOSFET. The current
versus gate overdrive voltage of M1 in an arbitrary operation
regime is then expressed as [16]: 2
0 1 2( ) n
DS OD gs gs gs n gsi V v A Av A v A v , (7)
( )
( )
( )1
!
n
DS OD gs
n n
gs
i V vA
n v
. (8)
where VOD is the DC gate overdrive voltage and vgs is the input
RF signal. Assume the RF signal vgs = vrf ·cos(ωt+θ) and vrf is
the amplitude of the input RF signal. When there are two
different RF input signals (any one of them can be zero also),
vgs1 and vgs2, the difference of the drain current is
1 1 2 2
2
0 1 1 1 1 2 1 1 1
1 1 1
2
0 1 2 2 2 2 2 2 2
2 2 2
1 1 1 1
( ) ( )
cos( ) cos( )
cos( )
cos( ) cos( )
cos( )
cos( )
DS DS OD gs DS OD gs
rf rf
n
n rf
rf rf
n
n rf
rf
i i V v i V v
A A v t A v t
A v t
A A v t A v t
A v t
A v t v
2 2
2 1 2
2 2 2
2 2
2 1 1 1 2 2 2
3 3
3 1 1 1 2 2 2
cos( )2
cos 2 2 cos 2 2
2
cos( ) cos( )
rf rf
rf
rf rf
rf rf
A v vt
A v t v t
A v t v t
. (9)
The difference of DC component in the drain current for
two different RF input signals is
2 2
2 1 2 4 4
4 1 2
5( )
2 8
rf rf
DS rf rf
A v vI A v v
. (10)
In Fig 4, the output DC voltage differences for two input
signals are
, 1 ,3 , 3
, 1 ,3 , 3
. 4( ) : ( ) ( )
. 4( ) : ( ) ( )
out out DS M L M DS M L
out out V DS M L M DS M L
Fig a V V I R r I R
Fig b V V A I R r I R
.(11)
where rm,3 is the drain source resistor of M3, Av is the voltage
gain provided by the embedded amplifier. The DC output of
the PD is a special case when Vrf2=0 in (9)-(11). The
theoretical analysis of the unknown parameters A2, A4··· can be
classified into two cases: the velocity saturation regime and the
subthreshold regime.
Velocity Saturation Regime
In a short-channel transistor, velocity saturation is the most
important secondary effect in the triode and saturation
regimes. The drain current accounting the velocity saturation
effect in a short channel transistor can be described as [17]: 2
2
2 3
2
( ) 12 2
5 71
2 4 4
oxDS OD gs
c
ox
c c c
C W xi V v x
L E L
C W x x xx
L E L E L E L
. (12)
cosOD rfx V v t (13)
where μ is the charge carrier mobility, Cox is the gate-oxide
capacitance per unit area, W and L are the width and length of
the transistor, respectively, and Ec is the critical electric field.
The unknown parameters in (10) can be obtained from (7), (8),
(12), and (13).
2 3
2,
3 15 351
2 2 2
ox OD OD ODv sat
C C C
C W V V VA
L E L E L E L
. (14)
If the higher order (n ≥ 4) terms in (10) are ignored, and
putting (14) into (10), the DC current difference of the drain
current caused by two different RF input signals can be
determined.
2 2
1 2
,
2 3
2 2
3 15 351
2 2 2
rf rfoxDS v sat
OD OD OD
C C C
v vC WI
L
V V V
E L E L E L
(15)
To achieve the maximum sensitivity, (15) should be as large
as possible when RL is fixed according to (11). In (15), when
VOD > Ec·L, VOD should be as large as possible. To keep the M1
in the saturation regime, we can estimate the range of gate bias
voltage Vb1 in Fig 4(a):
,3
1,min 1 1,max
,3
1 1 2 ( )
( )
dd L M ox
b th b th b
L M ox
WV R r C
LV V V V VW
R r CL
. (16)
In the 0.13 μm CMOS process for circuit implementation
we used, Vth = 0.45 V, μ · Cox / 2 ≈ 297 uA / V2. If W / L= 1.3
μm / 0.12 μm, Vdd =1.2 V, RL = 6000 Ω and ignore rM,3, then
Vb1, max = 0.67 V. The measurement results show that the
circuit in Fig 4(a) achieves maximum sensitivity when Vb1 ≈0.6
V (equal to the case in which rM,3 =8500 Ω). In design of the
circuit in Fig 4(b), the initial voltage of Vout- and Vout+ should
be close to 0.6 V.
Subthreshold Regime
When the input power is high enough, and Vout- < Vth,
transistor M1 enters the sub-threshold regime. Its drain current
can be expressed as [17]:
/
2 3
( ) 1 exp
1 11
2 6
x
mKT q DSDS OD gs S
T
S
vi V v I e
V
q x q x q xI
mKT mKT mKT
(17)
where IS and m are empirical parameters, K is the Boltzmann
constant, T is the temperature, q is the electron charge, and VT
is the threshold voltage. The A2 in the subthreshold regime can
then be obtained from (7), (8), and (17).
2, 2 3
1 1 1 3
2 6/ /
ODsub S
VA I
mKT q mKT q
(18)
Equation (18) also presents a positive relationship between A2
and gate overdrive voltage VOD.
The foregoing theoretical analysis can be used to guide the
PD design to get the maximum sensitivity. In the measurement
applications, the unknown parameters A2, A4··· can be obtained
by calibration.
In theory, the minimum detectable input signal level
depends upon the noise floor. Without considering the
matching networks in Fig 4 and if the circuits are perfectly
symmetric, the noise floor caused by the source impedance is -
174 dBm/Hz. In reality, the most important effects come from
the input networks. The estimated noise floor is -159 dBm/Hz
for Fig. 4(a) and -141 dBm/Hz for Fig 4(b). Even though the
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ultra-wide-band quasi-T-coil matching network in Fig 4(b)
causes more noise than that in Fig 4(a), it may not affect its
application in communication or measurement systems since
the noise floor is still very low, compared to the application
requirements.
IV. EXPERIMENTAL RESULTS
The circuits shown in Fig 4 are implemented in a 0.13 μm
CMOS process. The critical design parameters are shown in
Table I. The circuit layouts are arranged as symmetrically as
possible to minimize mismatch. In Fig 4(a), the PMOS
transistors M3 and M4 are changed to NMOS and Vb2 is
connected to Vdd directly to reduce the number of controlling
terminals. The die microphotographs are shown in Fig 5. The
active circuit areas in Fig 5(a) and (b) are 170×320 μm2 and
250×340 μm2, respectively. Throughout our measurements
with a 1.2 V power supply, the structure shown in Fig 4(a)
shows maximum sensitivity to the input power when Vb1 = 0.6
V. Thus, all of the following results are measured when Vb1 =
0.6 V. The static power consumption of the circuits in Fig 4 (a)
and Fig 4(b) are 0.12 mW and 0.1 mW respectively with a 1.2
V power supply.
(a) (b)
Fig. 5. (a) Die microphotograph of the circuit in Fig 4(a), (b) the circuit in
Fig 4(b).
Fig. 6. Measured S-Parameter of the fabricated circuits in Fig 4(a) (with R
matched) and in Fig 4 (b) with quasi T-coil network.
Fig 6 shows the measured S11 of the circuits in Fig 4. If -15
dB is considered as the maximum acceptable reflection
coefficient, the quasi T-coil matching network discussed in
Section II provides matching from 500 MHz to 20.5 GHz,
which is much wider than the matching frequency range with
resistors in Fig 4(a). TABLE I
CIRCUIT DESIGN PARAMETERS
Device Unit Designed
Value Device Unit
Designed
Value
M1, M2 μm / μm 1.3 / 0.12 M3, M4 μm / μm 13 / 0.12
C fF 60 C0 pF 20
R1,2,3 Ω 104 L nH 0.894
RL K Ω 6 R4 K Ω 20
Ra Ω 34 Rb Ω 16
(a)
(b)
Fig. 7. Measured output voltage versus input power of (a) Fig 4(a) and (b)
Fig 4(b).
Fig 7 shows the output voltage versus input power at
different frequencies. Fig 7(a) shows that the circuit in Fig 4(a)
operates from 2 GHz to 14 GHz with output response
difference less than 3 dB for a given input power as the
frequency is swept, while Fig 7(b) shows that the circuit in Fig
4(b) can operates from 500 MHz to 20 GHz. Fig 7(b) also
shows that when the input power is larger than -10 dBm, the
output voltage is almost linear as indicated by the arrow,
because the transistors in Fig 4(b) operate in the subthreshold
regime. From 500 MHz to 20 GHz, the output response
difference is less than 1.9 dB for a given input power in the
linear operation range as the arrow shown in Fig 7(b). The
optimal fitting curves in the linear regime are
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500 : 40 ( ) 885;
10 : 36 ( ) 711;
20 : 40 ( ) 775;
MHz output mv input power dB
GHz output mv input power dB
GHz output mv input power dB
. (18)
. .
.
calculated value measured valueerror ratio
calculated value
. (19)
The error ratios between the output and the optimal fitting
curves are less than ±1% for the linear operation range (about
20 dB input range) with the definition in (19). When the input
power is less than -10 dBm, the power detector transistors in
Fig 4(b) operate in the saturation regime. A comparison of the
curves in Fig 7(b) shows that when the transistors operate in
subthreshold regime the sensitivity is lower than that when in
the saturation regime. Experimental results show an
approximate improvement of 15 dB input dynamic range for
the circuit shown in Fig 4(b) as compared to Fig 4(a). The
negative values in Fig 7(b) are caused by the unperfected
symmetric and secondary effects of the transistors. It does not
affect its applications in measurement systems, since it can be
absorbed during the calibration procedure.
When the power supply voltage is varied from 1.2 V to 0.5
V, Fig 8(a) shows that the input dynamic range of the power
detector in Fig 4(a) decreases by 10 dB, while the dynamic
range of the power detector in Fig 4(b) is power supply
voltage independent. When the power supply is varied from
1.2 V to 0.5 V, the linear operation range expands at the
expense of lower sensitivity with a decrease in power supply.
A comparison of Fig 8(c) and (d) shows a dramatic reduction
in power consumption when the power supply is varied from
1.2 V to 0.5 V. The static power consumption of the circuit in
Fig 4(b) is only 2×10-4
mW, and this characteristic is very
useful for the applications in portable terminals. The peak in
Fig 8(d) is caused by the amplifier.
(a)
(b)
(c)
(d)
Fig. 8. At different Vdd power supplies, measured output voltage versus input
power of the circuit (a) Fig 4(a), (b) Fig 4(b); power consumptions versus
input power of the circuit (c) Fig 4(a), (d) Fig 4(b).
Table II is the comparison of this work with recent
publication results. This work achieves the maximum
sensitivity and largest input dynamic range from 500 MHz to
20 GHz.
TABLE II
PERFORMANCE COMPARISON WITH RECENT PUBLISHED PD
[11] [12] Fig 3(b)
Technology 0.13 μm
CMOS
0.18 μm
CMOS
0.13 μm
CMOS
Power
Consumption
0.18 mW 3.8 mW 0.1 mW @1.2 V
2-4 mW @0.5 V
Operating
Frequency
125 MHz -8.5
GHz
3.1 GHz -10.6
GHz
500 MHz – 20
GHz
Input dynamic
range
20 dB ~35 dB 47 dB
Linearity
Error For
Specified
Input Range
±0.5 dB for 18
dB
± 2.4 dB for
20 dB
< ±1% for ~20
dB
Flatness of
Frequency
Response
12 dB 1.8 dB 1.9 dB
Output
Sensitivity
~6.5 mV/dB ~4.3 mV/dB ~26.8 mV/dB
V. CONCLUSION
In this paper, we introduced a self-biased folded power
detector. Depending on input power level, the transistors work
in saturation or subthreshold regimes. To enhance the
sensitivity and expand the operating frequency range, an ultra-
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wide-band quasi T-coil matching network was designed and an
embedded amplifier was used. The operating frequency ranges
from 500 MHz to 20 GHz. The output response is nearly
frequency independent in the linear operation range, varying
by less than 1.9 dB for a fixed input power. The linearity error
in the linearity operation range is less than ±1%.
Though the linearity operation range is ~20 dB, the
detectable input dynamic range is up to 47 dB, which is very
useful in six-port communication and measurement systems
applications, since the input power levels of the measurement
port 3-6 may change dramatically when the input signal in port
2 varies. The nonlinearity operation range is also useful after
the calibration procedure in six-port systems.
ACKNOWLEDGMENT
The authors appreciate the help form Prof. L. Wilson
Pearson and Prof. John Komo in the department of Electrical
and Computer Engineering, Clemson University, USA. The
authors are grateful to MOSIS for fabricating the chips.
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