A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

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15.1: A 0.0066mm 2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase- Coupled Oscillator Using Edge-Injection Technique © 2014 IEEE International Solid-State Circuits Conference 0 of 42 A 0.0066mm 2 780mW Fully Synthesizable PLL with a Current Output DAC and an Interpolative Phase-Coupled Oscillator using Edge Injection Technique Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan

Transcript of A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

Page 1: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 0 of 42

A 0.0066mm2 780mW Fully Synthesizable

PLL with a Current Output DAC and an

Interpolative Phase-Coupled Oscillator

using Edge Injection Technique

Wei Deng, Dongsheng Yang, Tomohiro Ueno,

Teerachot Siriburanon, Satoshi Kondo,

Kenichi Okada, and Akira Matsuzawa

Tokyo Institute of Technology, Japan

Page 2: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 1 of 42

Outline• Motivation

• Concept of synthesizable analog circuits

• Synthesizable PLL

– Interpolative phase-coupled oscillator

– Standard-cell I-DAC

– Standard-cell varactor

– Edge injection

• Measurement Results

• Conclusion

Page 3: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 2 of 42

Motivation

• Synthesizable analog circuits– Portability

– Scalability

– Layout issues above 20nm

• Potential applications

– PLL

– ADC, DAC

– Wireless/Wireline transceivers

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 3 of 42

Synthesizable Analog Circuits

GDSDigital design flow

Commercial P&R tools…

HDL

module PLL (CLK, …, OUT)

endmodule

with a standard-cell library

without any custom-designed cellswithout manual placement

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 4 of 42

Issue: Layout Uncertainty

Ideal placement Actual placement

Unbalanced loading

No layout symmetry

A new analog-circuit architecture is required,

which tolerates layout impairment/uncertainty.

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 5 of 42

Conventional All-digital PLLs

• TDC-based architecture

–The layout uncertainty degrades TDC

and DCO linearity.

–Poor frequency resolution by

standard-cell design.

• Trade-off between layout integrity and

jitter performance

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 6 of 42

Proposed Synthesizable PLL

• Injection-locking topology

– Avoid TDC issues (linearity, power-resolution

trade-off)

• Circuit techniques

– Interpolative phase-coupled osc. & I-DAC

• Overcome phase imbalance

– A new varactor for fine resolution

• Low spur level

– Edge injection technique

• Relax severe timing design

Page 8: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 7 of 42

TOP Block Diagram

[W. Deng, et al., ISSCC 2013]

Pulse Edge• Interpolation

• Stdcell varactor

• Stdcell I-DAC

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 8 of 42

TOP Block Diagram

Pulse Edge• Interpolation

• Stdcell varactor

• Stdcell I-DAC

Feedforward phase locking

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 9 of 42

TOP Block Diagram

[W. Deng, et al., ISSCC 2013]

Pulse Edge• Interpolation

• Stdcell varactor

• Stdcell I-DAC

Feedback FLL for frequency tracking

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 10 of 42

Outline• Motivation

• Concept of synthesizable analog circuits

• Synthesizable PLL

– Interpolative phase-coupled oscillator

– Standard-cell I-DAC

– Standard-cell varactor

– Edge injection

• Measurement Results

• Conclusion

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 11 of 42

Block Diagram of DCO

[A. Matsumoto, et al., JSSC 2008]

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 12 of 42

Block Diagram of Oscillator 1

Osc. 1

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 13 of 42

Block Diagram of Oscillator 2

Osc. 2

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 14 of 42

Block Diagram of Oscillator 3

Osc. 3

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 15 of 42

Interpolative Phase-coupled Ring

PI: Phase

Interpolator

Page 17: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 16 of 42

Outline• Motivation

• Concept of synthesizable analog circuits

• Synthesizable PLL

– Interpolative phase-coupled oscillator

– Standard-cell I-DAC

– Standard-cell varactor

– Edge injection

• Measurement Results

• Conclusion

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 17 of 42

Conventional Coarse Tuning

Unbalanced loading at each stage.

[D. Sheng, et al., TCAS II 2007]

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 18 of 42

Coarse Tuning using DAC

DACn

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 19 of 42

Simple Voltage-output DAC

D0D1= 11 Vout= 0V

D0D1= 10 Vout= 0.5V

D0D1= 01 Vout= 0.5V

D0D1= 00 Vout= 1V

D0= 0 Vout= 1V

D0= 1 Vout= 0V

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 20 of 42

Model of V-linear DAC

• How to obtain a I-linear DAC?

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 21 of 42

Proposed I-linear DAC

• A feedback structure for forming a

current mirror.

D0

D1

D2

D3

1

1

Iout

×1

×2

×4

×8

Page 23: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 22 of 42

Proposed I-linear DAC (cont.)

1

...1

×2

D0

D1

D2

D3IDAC

D4

D4

×1

D4

D4

×4

D4

D4

×8

D4

D4

×1

×2

×4

×81

D0

D1

D2

D3

D4

D4

D4

D4

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 23 of 42

Simulation Result

Page 25: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 24 of 42

V-DAC VS I-DAC

0 4 8 12

Control Code

Cu

rren

t[m

A]

0.24

0.20

0.16

0.12

0 4 8 12

Control Code

Fre

qu

en

cy[G

Hz]

1.6

1.2

0.8

D4=1 D4=1

Page 26: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 25 of 42

Outline• Motivation

• Concept of synthesizable analog circuits

• Synthesizable PLL

– Interpolative phase-coupled oscillator

– Standard-cell I-DAC

– Standard-cell varactor

– Edge injection

• Measurement Results

• Conclusion

Page 27: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 26 of 42

Medium Tuning Capacitor

Vin

Conventional:

1.55ps@200MHz

[P.L. Chen, et al., TCAS II 2005]

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 27 of 42

Simulated Cmedium against Vin

0 0.2 0.4 0.6 0.8

4

8

12

16

Cm

ed

ium

[fF

]

Vin [V]

DM=1

DM=0

Miller effect

PMOS+offsetoffset

NMOS

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 28 of 42

Miller Effect Sensitivity

• Miller effect can be controlled by Vout.

Cin

[fF

]

Vin[V]0 0.2 0.4 0.6 0.8

4

8

12

16

VOUT=0.4V

VOUT=0.6V

VOUT=0.2V

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 29 of 42

Miller Effect Sensitivity (Cont.)

• A transient variation of VOUT can make a fine

capacitance difference in CIN.

t

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 30 of 42

Tuning Capacitors

0 10 20 30

Time[ps]

0 10 20 30

Time[ps]

Vin

[V]

VDD

Vin

[V]

VDD

4.8ps0.4ps

Vin

DM=1DM=0DF=0DF=1

Vin

(0.066ps×6)

(Proposed)

Page 32: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 31 of 42

Outline• Motivation

• Concept of synthesizable analog circuits

• Synthesizable PLL

– Interpolative phase-coupled oscillator

– Standard-cell I-DAC

– Standard-cell varactor

– Edge injection

• Measurement Results

• Conclusion

Page 33: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 32 of 42

Conventional Pulse Injection

Free-running

Injection Pulse

Injection locked

[B. Helal, et al., JSSC 2009]

• Severe timing design is required on the injection pulse width.

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 33 of 42

Edge InjectionVx

Inj.

window

Inj. edge

Vy

• Severe timing design is not required.

(1)

(2)

(3)

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 34 of 42

Design Procedure

Verilog netlist

(gate-level)

Verilog

RTL

Verilog netlist

(gate-level)

DCO DAC

Logic

Logic

Logic Synt. Tool

GDSII

P&R Tool

Netlist

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 35 of 42

Chip Microphotograph

Fully

Synthesized

110mm

60mm

CMOS 65nm

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 36 of 42

Phase Noise

10k 100k 1M 10M

-120

-80

-40

0

Offset Frequency[Hz]

Ph

as

e N

ois

e [

dB

c/H

z] Frequency: 900MHz

Integrating Jitter: 1.7ps

PDC: 780mW

Page 38: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 37 of 42

Measured Spur Level

N=6

1st Spur: -41 dBc

2nd Spur: -51 dBc

Edge Injection

(This work)

Pulse Injection

(Conventional)

N=6

1st Spur: -41 dBc

2nd Spur: -42 dBc

N: Multiplication factor

-42dBc-51dBc

Page 39: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 38 of 42

Layout Consideration

70m

m

DCO DCO

Hierarchical P&R

with synthesized

DCOs

130 mm

60m

m

110 mm

Fully synthesized

(proposed)

Integrating Jitter: 1.7ps

PDC: 780mW

FOM: -236.5 dB

Integrating Jitter: 2.32ps

PDC: 640mW

FOM: -234.6 dB

DCO DCO

Page 40: A 0.0066mm2 780μW Fully Synthesizable PLL with a Current Output ...

15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 39 of 42

Compar. of Synthesizable PLLsThis work

65nm

[1]

28nm

[2]

65nm

[3]

65nm

Power

[mW]0.78

@900MHz

13.7 @2.5GHz

3.1@250MHz

2.1@403MHz

Area

[mm2]0.0066 0.042 0.032 0.1

Integ.

Jitter [ps]1.7 N.A. 30 N.A.

RMS

Jitter [ps]2.8 3.2 N.A. 13.3

FOM [dB] -236.5 -218.6* -205.5 -214*W/ custom

cells?No No Yes Yes

Topology IL-base TDC-base TDC-base TDC-base

*FOM is calculated based on RMS jitter.

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 40 of 42

Performance Comparison

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 41 of 42

Conclusion

• Synthesizable analog circuit design

is proposed.

– By the digital design flow

– Without any manual placement

– Without any custom-designed cells

• Fully synthesized PLL

– Dual-loop injection-lock topology

– Current-output DAC

– Ultra-fine frequency resolution

– Interpolative-phase coupled oscillator

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15.1: A 0.0066mm2 780mW Fully Synthesizable PLL with a Current-Output DAC and an Interpolative Phase-

Coupled Oscillator Using Edge-Injection Technique© 2014 IEEE International Solid-State Circuits Conference 42 of 42

Acknowledgement

This work was partially supported by

STARC, SCOPE, MIC, MEXT, Canon

Foundation, and VDEC in collaboration

with Synopsys, Inc., Cadence Design

Systems, Inc., and Agilent Technologies

Japan, Ltd.