78K0R/KG3 16-bit Single-Chip Microcontrollers UD · In the case of a device that uses different...
Transcript of 78K0R/KG3 16-bit Single-Chip Microcontrollers UD · In the case of a device that uses different...
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Document No. U17894EJ6V0UD00 (6th edition) Date Published June 2007 NS
Printed in Japan 2006
PD78F1162 PD78F1163 PD78F1164 PD78F1165 PD78F1166 PD78F1167 PD78F1168
78K0R/KG3 16-bit Single-Chip Microcontrollers
Users Manual
The 78K0R/KG3 has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product after the on-chip debug function has been used.
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[MEMO]
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
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Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
EEPROM is a trademark of NEC Electronics Corporation.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.
The information in this document is current as of June, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features.NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application.
(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries."NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audioand visual equipment, home electronic appliances, machine tools, personal electronic equipmentand industrial robots.Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support).Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
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INTRODUCTION
Readers This manual is intended for user engineers who wish to understand the functions of the
78K0R/KG3 and design and develop application systems and programs for these
devices.
The target products are as follows.
78K0R/KG3: PD78F1162, 78F1163, 78F1164, 78F1165, 78F1166, 78F1167, 78F1168
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The 78K0R/KG3 manual is separated into two parts: this manual and the instructions
edition (common to the 78K0R Microcontroller Series).
78K0R/KG3
Users Manual
(This Manual)
78K0R Microcontroller
Users Manual
Instructions
Pin functions Internal block functions Interrupts Other on-chip peripheral functions Electrical specifications
CPU functions Instruction set Explanation of each instruction
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark shows major
revised points. The revised points can be easily searched by copying an in
the PDF file and specifying it in the Find what: field.
How to interpret the register format: For a bit number enclosed in angle brackets, the bit name is defined as a
reserved word in the RA78K0R, and is defined as an sfr variable using the
#pragma sfr directive in the CC78K0R.
To know details of the 78K0R Series instructions: Refer to the separate document 78K0R Microcontroller Instructions Users
Manual (U17792E).
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Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: (overscore over pin and signal name) Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary ... or B Decimal ... Hexadecimal ...H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
78K0R/KG3 Users Manual This manual
78K0R Microcontroller Instructions Users Manual U17792E
Documents Related to Development Tools (Software) (Users Manuals)
Document Name Document No.
Operation U17838E CC78K0R Ver. 1.00 C Compiler
Language U17837E
Operation U17836E RA78K0R Ver. 1.00 Assembler Package
Language U17835E
SM+ System Simulator Operation U18010E
PM+ Ver. 6.20 U17990E
ID78K0R-QB Ver. 3.20 Integrated Debugger Operation U17839E
Documents Related to Development Tools (Hardware) (Users Manuals)
Document Name Document No.
QB-MINI2 On-Chip Debug Emulator with Programming Function U18371E
QB-78K0RKX3 In-Circuit Emulator U17866E
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP4 Flash Memory Programmer Users Manual U15260E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
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Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE Products and Packages X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the Semiconductor Device Mount Manual website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
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CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 17
1.1 Features......................................................................................................................................... 17 1.2 Applications .................................................................................................................................. 18 1.3 Ordering Information.................................................................................................................... 18 1.4 Pin Configuration (Top View) ...................................................................................................... 19 1.5 78K0R Microcontroller Lineup .................................................................................................... 22 1.6 Block Diagram .............................................................................................................................. 23 1.7 Outline of Functions..................................................................................................................... 24
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 26
2.1 Pin Function List .......................................................................................................................... 26 2.2 Description of Pin Functions ...................................................................................................... 32
2.2.1 P00 to P06 (port 0) ........................................................................................................................... 32 2.2.2 P10 to P17 (port 1) ........................................................................................................................... 33 2.2.3 P20 to P27 (port 2) ........................................................................................................................... 34 2.2.4 P30, P31 (port 3) .............................................................................................................................. 34 2.2.5 P40 to P47 (port 4) ........................................................................................................................... 35 2.2.6 P50 to P57 (port 5) ........................................................................................................................... 36 2.2.7 P60 to P67 (port 6) ........................................................................................................................... 37 2.2.8 P70 to P77 (port 7) ........................................................................................................................... 37 2.2.9 P80 to P87 (port 8) ........................................................................................................................... 38 2.2.10 P110, P111 (port 11) ...................................................................................................................... 38 2.2.11 P120 to P124 (port 12) ................................................................................................................... 38 2.2.12 P130, P131 (port 13) ...................................................................................................................... 39 2.2.13 P140 to P145 (port 14) ................................................................................................................... 40 2.2.14 P150 to P157 (port 15) ................................................................................................................... 41 2.2.15 AVREF0 ............................................................................................................................................ 41 2.2.16 AVREF1 ............................................................................................................................................ 41 2.2.17 AVSS ............................................................................................................................................... 41 2.2.18 RESET ........................................................................................................................................... 41 2.2.19 REGC............................................................................................................................................. 42 2.2.20 VDD, EVDD0, EVDD1 .......................................................................................................................... 42 2.2.21 VSS, EVSS0, EVSS1 ........................................................................................................................... 42 2.2.22 FLMD0 ........................................................................................................................................... 42
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 43
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 48
3.1 Memory Space .............................................................................................................................. 48 3.1.1 Internal program memory space ...................................................................................................... 58 3.1.2 Mirror area........................................................................................................................................ 60 3.1.3 Internal data memory space............................................................................................................. 61 3.1.4 Special function register (SFR) area ................................................................................................ 62 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ....................... 62
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3.1.6 Data memory addressing..................................................................................................................63 3.2 Processor Registers .................................................................................................................... 70
3.2.1 Control registers................................................................................................................................70 3.2.2 General-purpose registers ................................................................................................................72 3.2.3 ES and CS registers .........................................................................................................................74 3.2.4 Special function registers (SFRs)......................................................................................................75 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)............................81
3.3 Instruction Address Addressing ................................................................................................ 87 3.3.1 Relative addressing ..........................................................................................................................87 3.3.2 Immediate addressing.......................................................................................................................87 3.3.3 Table indirect addressing..................................................................................................................88 3.3.4 Register direct addressing ................................................................................................................89
3.4 Addressing for Processing Data Addresses............................................................................. 90 3.4.1 Implied addressing............................................................................................................................90 3.4.2 Register addressing..........................................................................................................................90 3.4.3 Direct addressing..............................................................................................................................91 3.4.4 Short direct addressing .....................................................................................................................92 3.4.5 SFR addressing ................................................................................................................................93 3.4.6 Register indirect addressing .............................................................................................................94 3.4.7 Based addressing .............................................................................................................................95 3.4.8 Based indexed addressing................................................................................................................98 3.4.9 Stack addressing ..............................................................................................................................99
CHAPTER 4 PORT FUNCTIONS......................................................................................................... 100
4.1 Port Functions............................................................................................................................ 100 4.2 Port Configuration ..................................................................................................................... 103
4.2.1 Port 0 ..............................................................................................................................................104 4.2.2 Port 1 ..............................................................................................................................................110 4.2.3 Port 2 ..............................................................................................................................................116 4.2.4 Port 3 ..............................................................................................................................................118 4.2.5 Port 4 ..............................................................................................................................................119 4.2.6 Port 5 ..............................................................................................................................................128 4.2.7 Port 6 ..............................................................................................................................................130 4.2.8 Port 7 ..............................................................................................................................................133 4.2.9 Port 8 ..............................................................................................................................................134 4.2.10 Port 11 ..........................................................................................................................................135 4.2.11 Port 12 ..........................................................................................................................................136 4.2.12 Port 13 ..........................................................................................................................................139 4.2.13 Port 14 ..........................................................................................................................................141 4.2.14 Port 15 ..........................................................................................................................................145
4.3 Registers Controlling Port Function ........................................................................................ 146 4.4 Port Function Operations.......................................................................................................... 153
4.4.1 Writing to I/O port............................................................................................................................153 4.4.2 Reading from I/O port .....................................................................................................................153 4.4.3 Operations on I/O port ....................................................................................................................153 4.4.4 Connecting to external device with different potential (2.5V, 3 V) ...................................................154
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 156 4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 159
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CHAPTER 5 EXTERNAL BUS INTERFACE ...................................................................................... 160
5.1 Functions of External Bus Interface......................................................................................... 160 5.2 Registers Controlling External Bus Interface Functions ....................................................... 166 5.3 Setting Port Mode Register and Output Latch ........................................................................ 169 5.4 Number of Instruction Wait Clocks or Data Access ............................................................... 170 5.5 Number of Instruction Wait Clocks for Fetch Access ............................................................ 170 5.6 Timing of External Bus Interface Function.............................................................................. 171
5.6.1 Multiplexed bus mode .....................................................................................................................172 5.6.2 Separate bus mode.........................................................................................................................176
5.7 Example of Connection to Memory .......................................................................................... 180 5.7.1 Connection of external logic (ASIC, etc.).........................................................................................180 5.7.2 Connection of synchronous memory...............................................................................................180 5.7.3 Connection of asynchronous memory.............................................................................................181
CHAPTER 6 CLOCK GENERATOR .................................................................................................... 182
6.1 Functions of Clock Generator................................................................................................... 182 6.2 Configuration of Clock Generator ............................................................................................ 183 6.3 Registers Controlling Clock Generator.................................................................................... 185 6.4 System Clock Oscillator ............................................................................................................ 199
6.4.1 X1 oscillator.....................................................................................................................................199 6.4.2 XT1 oscillator ..................................................................................................................................199 6.4.3 Internal high-speed oscillator ..........................................................................................................202 6.4.4 Internal low-speed oscillator............................................................................................................202 6.4.5 Prescaler .........................................................................................................................................202
6.5 Clock Generator Operation ....................................................................................................... 203 6.6 Controlling Clock........................................................................................................................ 207
6.6.1 Example of controlling high-speed system clock.............................................................................207 6.6.2 Example of controlling internal high-speed oscillation clock............................................................210 6.6.3 Example of controlling subsystem clock..........................................................................................212 6.6.4 Example of controlling internal low-speed oscillation clock .............................................................214 6.6.5 CPU clock status transition diagram................................................................................................215 6.6.6 Condition before changing CPU clock and processing after changing CPU clock ..........................220 6.6.7 Time required for switchover of CPU clock and main system clock ................................................221 6.6.8 Conditions before clock oscillation is stopped .................................................................................222
CHAPTER 7 TIMER ARRAY UNIT...................................................................................................... 223
7.1 Functions of Timer Array Unit................................................................................................... 223 7.1.1 Functions of each channel when it operates independently ............................................................223 7.1.2 Functions of each channel when it operates with another channel .................................................224 7.1.3 LIN-bus supporting function (channel 7 only) ..................................................................................224
7.2 Configuration of Timer Array Unit ............................................................................................ 225 7.3 Registers Controlling Timer Array Unit.................................................................................... 230 7.4 Channel Output (TO0n pin) Control.......................................................................................... 251
7.4.1 TO0n pin output circuit configuration...............................................................................................251 7.4.2 TO0n Pin Output Setting .................................................................................................................252 7.4.3 Cautions on Channel Output Operation ..........................................................................................252 7.4.4 Collective manipulation of TO0n bits ...............................................................................................256
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7.4.5 Timer Interrupt and TO0n Pin Output at Operation Start ................................................................257 7.5 Channel Input (TI0n Pin) Control .............................................................................................. 258
7.5.1 TI0n edge detection circuit ..............................................................................................................258 7.6 Basic Function of Timer Array Unit.......................................................................................... 259
7.6.1 Overview of single-operation function and combination operation function ....................................259 7.6.2 Basic rules of combination operation function.................................................................................259 7.6.3 Applicable range of basic rules of combination operation function..................................................260
7.7 Operation of Timer Array Unit as Independent Channel........................................................ 261 7.7.1 Operation as interval timer/square wave output..............................................................................261 7.7.2 Operation as external event counter ...............................................................................................265 7.7.3 Operation as frequency divider .......................................................................................................268 7.7.4 Operation as input pulse interval measurement..............................................................................272 7.7.5 Operation as input signal high-/low-level width measurement ........................................................276
7.8 Operation of Plural Channels of Timer Array Unit.................................................................. 280 7.8.1 Operation as PWM function ............................................................................................................280 7.8.2 Operation as one-shot pulse output function...................................................................................287 7.8.3 Operation as multiple PWM output function ....................................................................................294
CHAPTER 8 REAL-TIME COUNTER .................................................................................................. 301
8.1 Functions of Real-Time Counter............................................................................................... 301 8.2 Configuration of Real-Time Counter ........................................................................................ 301 8.3 Registers Controlling Real-Time Counter ............................................................................... 303 8.4 Real-Time Counter Operation ................................................................................................... 315
8.4.1 Starting operation of real-time counter ............................................................................................315 8.4.2 Reading/writing real-time counter ...................................................................................................316 8.4.3 Setting alarm of real-time counter ...................................................................................................318
CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 319
9.1 Functions of Watchdog Timer .................................................................................................. 319 9.2 Configuration of Watchdog Timer............................................................................................ 320 9.3 Register Controlling Watchdog Timer ..................................................................................... 321 9.4 Operation of Watchdog Timer................................................................................................... 322
9.4.1 Controlling operation of watchdog timer..........................................................................................322 9.4.2 Setting overflow time of watchdog timer .........................................................................................323 9.4.3 Setting window open period of watchdog timer...............................................................................324 9.4.4 Setting watchdog timer interval interrupt .........................................................................................325
CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 326
10.1 Functions of Clock Output/Buzzer Output Controller.......................................................... 326 10.2 Configuration of Clock Output/Buzzer Output Controller ................................................... 327 10.3 Registers Controlling Clock Output/Buzzer Output Controller........................................... 327 10.4 Operations of Clock Output/Buzzer Output Controller ........................................................ 329
10.4.1 Operation as output pin.................................................................................................................329
CHAPTER 11 A/D CONVERTER ......................................................................................................... 330
11.1 Function of A/D Converter ...................................................................................................... 330 11.2 Configuration of A/D Converter .............................................................................................. 331
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11.3 Registers Used in A/D Converter............................................................................................ 333 11.4 A/D Converter Operations ....................................................................................................... 341
11.4.1 Basic operations of A/D converter .................................................................................................341 11.4.2 Input voltage and conversion results .............................................................................................343 11.4.3 A/D converter operation mode ......................................................................................................344
11.5 How to Read A/D Converter Characteristics Table............................................................... 346 11.6 Cautions for A/D Converter ..................................................................................................... 348
CHAPTER 12 D/A CONVERTER ......................................................................................................... 352
12.1 Function of D/A Converter....................................................................................................... 352 12.2 Configuration of D/A Converter .............................................................................................. 352 12.3 Registers Used in D/A Converter............................................................................................ 353 12.4 Operation of D/A Converter..................................................................................................... 355
12.4.1 Operation in normal mode.............................................................................................................355 12.4.2 Operation in real-time output mode...............................................................................................355 12.4.3 Cautions ........................................................................................................................................356
CHAPTER 13 SERIAL ARRAY UNIT.................................................................................................. 357
13.1 Functions of Serial Array Unit................................................................................................. 357 13.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI20) ............................................................................357 13.1.2 UART (UART0, UART1, UART2, UART3) ....................................................................................358 13.1.3 Simplified I2C (IIC10, IIC20)...........................................................................................................358
13.2 Configuration of Serial Array Unit .......................................................................................... 359 13.3 Registers Controlling Serial Array Unit ................................................................................. 364 13.4 Operation stop mode ............................................................................................................... 386
13.4.1 Stopping the operation by units.....................................................................................................386 13.4.2 Stopping the operation by channels ..............................................................................................387
13.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI20) Communication ................... 389 13.5.1 Master transmission ......................................................................................................................390 13.5.2 Master reception ...........................................................................................................................399 13.5.3 Master transmission/reception ......................................................................................................405 13.5.4 Slave transmission ........................................................................................................................413 13.5.5 Slave reception .............................................................................................................................422 13.5.6 Slave transmission/reception ........................................................................................................428 13.5.7 Calculating transfer clock frequency..............................................................................................437
13.6 Operation of UART (UART0, UART1, UART2, UART3) Communication ............................. 439 13.6.1 UART transmission .......................................................................................................................440 13.6.2 UART reception.............................................................................................................................450 13.6.3 LIN transmission ...........................................................................................................................457 13.6.4 LIN reception.................................................................................................................................460 13.6.5 Calculating baud rate ....................................................................................................................465
13.7 Operation of Simplified I2C (IIC10, IIC20) Communication ................................................... 469 13.7.1 Address field transmission ............................................................................................................470 13.7.2 Data transmission..........................................................................................................................475 13.7.3 Data reception...............................................................................................................................478 13.7.4 Stop condition generation..............................................................................................................481 13.7.5 Calculating transfer rate ................................................................................................................482
13.8 Processing Procedure in Case of Error ................................................................................. 485
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13.9 Relationship Between Register Settings and Pins............................................................... 487
CHAPTER 14 SERIAL INTERFACE IIC0 ........................................................................................... 494
14.1 Functions of Serial Interface IIC0 ........................................................................................... 494 14.2 Configuration of Serial Interface IIC0..................................................................................... 497 14.3 Registers to Controlling Serial Interface IIC0........................................................................ 500 14.4 I2C Bus Mode Functions .......................................................................................................... 512
14.4.1 Pin configuration ...........................................................................................................................512 14.5 I2C Bus Definitions and Control Methods .............................................................................. 513
14.5.1 Start conditions .............................................................................................................................513 14.5.2 Addresses .....................................................................................................................................514 14.5.3 Transfer direction specification .....................................................................................................514 14.5.4 Transfer clock setting method .......................................................................................................515 14.5.5 Acknowledge (ACK)......................................................................................................................516 14.5.6 Stop condition ...............................................................................................................................518 14.5.7 Wait...............................................................................................................................................519 14.5.8 Canceling wait...............................................................................................................................521 14.5.9 Interrupt request (INTIIC0) generation timing and wait control......................................................522 14.5.10 Address match detection method................................................................................................523 14.5.11 Error detection ............................................................................................................................523 14.5.12 Extension code ...........................................................................................................................523 14.5.13 Arbitration....................................................................................................................................524 14.5.14 Wakeup function .........................................................................................................................525 14.5.15 Communication reservation ........................................................................................................526 14.5.16 Cautions......................................................................................................................................530 14.5.17 Communication operations .........................................................................................................531 14.5.18 Timing of I2C interrupt request (INTIIC0) occurrence ..................................................................539
14.6 Timing Charts ........................................................................................................................... 560
CHAPTER 15 MULTIPLIER .................................................................................................................. 567
15.1 Functions of Multiplier............................................................................................................. 567 15.2 Configuration of Multiplier ...................................................................................................... 568 15.3 Operation of Multiplier............................................................................................................. 569
CHAPTER 16 DMA CONTROLLER..................................................................................................... 570
16.1 Functions of DMA Controller .................................................................................................. 570 16.2 Configuration of DMA Controller............................................................................................ 571 16.3 Registers to Controlling DMA Controller............................................................................... 574 16.4 Operation of DMA Controller .................................................................................................. 577
16.4.1 Operation procedure .....................................................................................................................577 16.4.2 Transfer mode...............................................................................................................................578 16.4.3 Termination of DMA transfer .........................................................................................................578
16.5 Example of Setting of DMA Controller................................................................................... 579 16.5.1 CSI consecutive transmission .......................................................................................................579 16.5.2 Consecutive capturing of A/D conversion results..........................................................................581 16.5.3 UART consecutive reception + ACK transmission ........................................................................583 16.5.4 Holding DMA transfer pending by DWAITn...................................................................................585
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16.5.5 Forced termination by software .....................................................................................................586 16.6 Cautions on Using DMA Controller ........................................................................................ 587
CHAPTER 17 INTERRUPT FUNCTIONS ............................................................................................ 589
17.1 Interrupt Function Types ......................................................................................................... 589 17.2 Interrupt Sources and Configuration ..................................................................................... 590 17.3 Registers Controlling Interrupt Functions............................................................................. 593 17.4 Interrupt Servicing Operations ............................................................................................... 603
17.4.1 Maskable interrupt acknowledgment .............................................................................................603 17.4.2 Software interrupt request acknowledgment .................................................................................605 17.4.3 Multiple interrupt servicing.............................................................................................................606 17.4.4 Interrupt request hold ....................................................................................................................609
CHAPTER 18 KEY INTERRUPT FUNCTION ..................................................................................... 610
18.1 Functions of Key Interrupt ...................................................................................................... 610 18.2 Configuration of Key Interrupt ................................................................................................ 610 18.3 Register Controlling Key Interrupt ......................................................................................... 611
CHAPTER 19 STANDBY FUNCTION .................................................................................................. 612
19.1 Standby Function and Configuration..................................................................................... 612 19.1.1 Standby function ...........................................................................................................................612 19.1.2 Registers controlling standby function...........................................................................................612
19.2 Standby Function Operation ................................................................................................... 615 19.2.1 HALT mode ...................................................................................................................................615 19.2.2 STOP mode ..................................................................................................................................620
CHAPTER 20 RESET FUNCTION........................................................................................................ 626
20.1 Register for Confirming Reset Source................................................................................... 634
CHAPTER 21 POWER-ON-CLEAR CIRCUIT...................................................................................... 635
21.1 Functions of Power-on-Clear Circuit...................................................................................... 635 21.2 Configuration of Power-on-Clear Circuit ............................................................................... 636 21.3 Operation of Power-on-Clear Circuit ...................................................................................... 636 21.4 Cautions for Power-on-Clear Circuit ...................................................................................... 639
CHAPTER 22 LOW-VOLTAGE DETECTOR ....................................................................................... 641
22.1 Functions of Low-Voltage Detector........................................................................................ 641 22.2 Configuration of Low-Voltage Detector ................................................................................. 642 22.3 Registers Controlling Low-Voltage Detector......................................................................... 642 22.4 Operation of Low-Voltage Detector ........................................................................................ 647
22.4.1 When used as reset ......................................................................................................................648 22.4.2 When used as interrupt .................................................................................................................654
22.5 Cautions for Low-Voltage Detector ........................................................................................ 660
-
Users Manual U17894EJ6V0UD 15
CHAPTER 23 REGULATOR ................................................................................................................. 664
23.1 Regulator Overview ................................................................................................................ 664 23.2 Registers Controlling Regulator............................................................................................ 664
CHAPTER 24 OPTION BYTE............................................................................................................... 666
24.1 Functions of Option Bytes ...................................................................................................... 666 24.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) .........................................................666 24.1.2 On-chip debug option byte (000C3H/ 010C3H) ............................................................................667
24.2 Format of User Option Byte .................................................................................................... 667 24.3 Format of On-chip Debug Option Byte .................................................................................. 669 24.4 Setting of Option Byte ............................................................................................................. 669
CHAPTER 25 FLASH MEMORY.......................................................................................................... 670
25.1 Writing with Flash Memory Programmer............................................................................... 670 25.2 Programming Environment..................................................................................................... 673 25.3 Communication Mode.............................................................................................................. 673 25.4 Connection of Pins on Board.................................................................................................. 674
25.4.1 FLMD0 pin ....................................................................................................................................674 25.4.2 TOOL0 pin ....................................................................................................................................675 25.4.3 RESET pin ....................................................................................................................................675 25.4.4 Port pins........................................................................................................................................676 25.4.5 REGC pin......................................................................................................................................676 25.4.6 X1 and X2 pins..............................................................................................................................676 25.4.7 Power supply ................................................................................................................................676
25.5 Registers that Control Flash Memory .................................................................................... 676 25.6 Programming Method .............................................................................................................. 677
25.6.1 Controlling flash memory ..............................................................................................................677 25.6.2 Flash memory programming mode ...............................................................................................677 25.6.3 Selecting communication mode ....................................................................................................678 25.6.4 Communication commands...........................................................................................................678
25.7 Security Settings...................................................................................................................... 680 25.8 Flash Memory Programming by Self-Programming............................................................. 682
25.8.1 Boot swap function........................................................................................................................684 25.8.2 Flash shield window function ........................................................................................................686
CHAPTER 26 ON-CHIP DEBUG FUNCTION..................................................................................... 687
26.1 Connecting QB-MINI2 to 78K0R/KG3 ..................................................................................... 687 26.2 On-Chip Debug Security ID ..................................................................................................... 688 26.3 Securing of user resources..................................................................................................... 688
CHAPTER 27 BCD CORRECTION CIRCUIT ..................................................................................... 690
27.1 BCD Correction Circuit Function............................................................................................ 690 27.2 Registers Used by BCD Correction Circuit ........................................................................... 690 27.3 BCD Correction Circuit Operation.......................................................................................... 691
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Users Manual U17894EJ6V0UD 16
CHAPTER 28 INSTRUCTION SET........................................................................................................ 693
28.1 Conventions Used in Operation List ...................................................................................... 693 28.1.1 Operand identifiers and specification methods..............................................................................693 28.1.2 Description of operation column....................................................................................................694 28.1.3 Description of flag operation column .............................................................................................695 28.1.4 PREFIX Instruction........................................................................................................................695
28.2 Operation List ........................................................................................................................... 696
CHAPTER 29 ELECTRICAL SPECIFICATIONS................................................................................. 713
CHAPTER 30 PACKAGE DRAWINGS ................................................................................................. 765
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 767
A.1 Software Package ...................................................................................................................... 770 A.2 Language Processing Software ............................................................................................... 770 A.3 Control Software........................................................................................................................ 771 A.4 Flash Memory Programming Tools.......................................................................................... 771
A.4.1 When using flash memory programmer FG-FP4, FL-PR4, FG-FP5 and FL-PR5 ...........................771 A.4.2 When using on-chip debug emulator with programming function QB-MINI2...................................772
A.5 Debugging Tools (Hardware).................................................................................................... 772 A.5.1 When using in-circuit emulator QB-78K0RKX3...............................................................................772 A.5.2 When using on-chip debug emulator with programming function QB-MINI2...................................773
A.6 Debugging Tools (Software)..................................................................................................... 773
APPENDIX B REVISION HISTORY ..................................................................................................... 774
B.1 Major Revisions in This Edition ............................................................................................... 774 B.2 Revision History of Preceding Editions .................................................................................. 778
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Users Manual U17894EJ6V0UD 17
CHAPTER 1 OUTLINE
1.1 Features
Minimum instruction execution time can be changed from high speed (0.05 s: @ 20 MHz operation with high-speed system clock) to ultra low-speed (61 s: @ 32.768 kHz operation with subsystem clock)
General-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) ROM, RAM capacities
Item
Part Number
Program Memory (ROM)
Data Memory (RAM)
PD78F1162 64 KB 4 KB PD78F1163 96 KB 6 KB PD78F1164 128 KB 8 KB
PD78F1165 192 KB 10 KB PD78F1166 256 KB 12 KB
PD78F1167Note 384 KB 24 KB PD78F1168Note
Flash memory
512 KB 30 KB
Note Under development
On-chip single-power-supply flash memory (with prohibition of chip erase/block erase/writing function)
Self-programming (with boot swap function/flash shield window function)
On-chip debug function
On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
On-chip watchdog timer (operable with the on-chip internal low-speed oscillation clock)
On-chip multiplier (16 bits 16 bits) On-chip key interrupt function
On-chip clock output/buzzer output controller
On-chip BCD adjustment
I/O ports: 88 (N-ch open drain: 4)
Timer: 10 channels
16-bit timer: 8 channels Watchdog timer: 1 channel Real-time counter: 1 channel
Serial interface
CSI: 2 channels/UART: 1 channel CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel UART (LIN-bus supported): 1 channel I2C: 1 channel
10-bit resolution A/D converter (AVREF0 = 2.3 to 5.5 V): 16 channels
8-bit resolution D/A converter (AVREF1 = 1.8 to 5.5 V): 2 channels
Power supply voltage: VDD = 1.8 to 5.5 V
Operating ambient temperature: TA = 40 to +85C
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CHAPTER 1 OUTLINE
Users Manual U17894EJ6V0UD 18
1.2 Applications
Home appliances
Laser printer motors Clothes washers Air conditioners Refrigerators
Home audio systems
Digital cameras, digital video cameras
1.3 Ordering Information
Flash memory version
Part Number Package PD78F1162GF-GAS-AX 100-pin plastic LQFP (14 20) PD78F1163GF-GAS-AX 100-pin plastic LQFP (14 20) PD78F1164GF-GAS-AX 100-pin plastic LQFP (14 20) PD78F1165GF-GAS-AX 100-pin plastic LQFP (14 20) PD78F1166GF-GAS-AX 100-pin plastic LQFP (14 20) PD78F1167GF-GAS-AX Note 100-pin plastic LQFP (14 20) PD78F1168GF-GAS-AX Note 100-pin plastic LQFP (14 20) PD78F1162GC-UEU-AX 100-pin plastic LQFP (14 14) PD78F1163GC-UEU-AX 100-pin plastic LQFP (14 14) PD78F1164GC-UEU-AX 100-pin plastic LQFP (14 14) PD78F1165GC-UEU-AX 100-pin plastic LQFP (14 14) PD78F1166GC-UEU-AX 100-pin plastic LQFP (14 14) PD78F1167GC-UEU-AX Note 100-pin plastic LQFP (14 14) PD78F1168GC-UEU-AX Note 100-pin plastic LQFP (14 14)
Note Under development
Caution The 78K0R/KG3 has an on-chip debug function. Do not use this product for mass production,
because its reliability cannot be guaranteed after the on-chip debug function has been used, with
respect to the number of times the flash memory can be rewritten. NEC Electronics does not
accept complaints about this product after the on-chip debug function has been used.
-
CHAPTER 1 OUTLINE
Users Manual U17894EJ6V0UD 19
1.4 Pin Configuration (Top View)
100-pin plastic LQFP (14 20)
P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK20/SCL20 P143/SI20/RxD2/SDA20 P144/SO20/TxD2 P145/TI07/TO07 P00/TI00 P01/TO00 P02/SO10/TxD1 P03/SI10/RxD1/SDA10 P04/SCK10/SCL10 P131/TI06/TO06 P130 P20/ANI0 P21/ANI1 P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P150/ANI8 P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 P157/ANI15 AVSS
P50
/EX
8 P
51/E
X9
P52
/EX
10
P53
/EX
11
P54
/EX
12
P55
/EX
13
P56
/EX
14
P57
/EX
15
P17
/EX
31/T
I02/
TO
02
P16
/EX
30/T
I01/
TO
01/IN
TP
5 P
15/E
X29
/RT
CD
IV/R
TC
CL
P14
/EX
28/R
xD3
P13
/EX
27/T
xD3
P12
/EX
26/S
O00
/TxD
0 P
11/E
X25
/SI0
0/R
xD0
P10
/EX
24/S
CK
00
AV
RE
F1
P11
0/A
NO
0 P
111/
AN
O1
AV
RE
F0
EV
DD
0
VD
D
EV
SS
0 V
SS
RE
GC
P12
1/X
1 P
122/
X2/
EX
CLK
FLM
D0
P12
3/X
T1
P12
4/X
T2
RE
SE
T P
40/T
OO
L0 P
41/T
OO
L1 P
42/T
I04/
TO
04 P
43/S
CK
01 P
44/S
I01
P45
/SO
01 P
46/IN
TP
1/T
I05/
TO
05 P
47/IN
TP
2 P
120/
INT
P0/
EX
LVI
P60/SCL0 P61/SDA0
P62 P63
P31/TI03/TO03/INTP4 P64/RD
P65/WR0 P66/WR1
P67/ASTB P77/EX23/KR7/INTP11 P76/EX22/KR6/INTP10 P75/EX21/KR5/INTP9 P74/EX20/KR4/INTP8
P73/EX19/KR3 P72/EX18/KR2 P71/EX17/KR1 P70/EX16/KR0
P06/WAIT P05/CLKOUT
EVSS1 P80/EX0 P81/EX1 P82/EX2 P83/EX3 P84/EX4 P85/EX5 P86/EX6 P87/EX7
P30/INTP3/RTC1HZ EVDD1
807978777675747372717069686766656463626160595857565554535251
123456789101112131415161718192021222324252627282930
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Cautions 1. Make AVSS the same potential as EVSS0, EVSS1, and VSS.
2. Make EVDD0 and EVDD1 the same potential as VDD.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remark When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the two EVDD pins and connect the
two EVSS pins to separate ground lines.
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CHAPTER 1 OUTLINE
Users Manual U17894EJ6V0UD 20
100-pin plastic LQFP (14 14)
12345678910111213141516171819202122232425
P157/ANI15AVSSAVREF0P111/ANO1P110/ANO0AVREF1P10/EX24/SCK00P11/EX25/SI00/RxD0P12/EX26/SO00/TxD0P13/EX27/TxD3P14/EX28/RxD3P15/EX29/RTCDIV/RTCCLP16/EX30/TI01/TO01/INTP5P17/EX31/TI02/TO02P57/EX15P56/EX14P55/EX13P54/EX12P53/EX11P52/EX10P51/EX9P50/EX8EVDD1P30/INTP3/RTC1HZP87/EX7
P14
3/S
I20/
RxD
2/S
DA
20P
144/
SO
20/T
xD2
P14
5/T
I07/
TO
07P
00/T
I00
P01
/TO
00P
02/S
O10
/TxD
1P
03/S
I10/
RxD
1/S
DA
10P
04/S
CK
10/S
CL1
0P
131/
TI0
6/T
O06
P13
0P
20/A
NI0
P21
/AN
I1P
22/A
NI2
P23
/AN
I3P
24/A
NI4
P25
/AN
I5P
26/A
NI6
P27
/AN
I7P
150/
AN
I8P
151/
AN
I9P
152/
AN
I10
P15
3/A
NI1
1P
154/
AN
I12
P15
5/A
NI1
3P
156/
AN
I14
P62
P63
P31
/TI0
3/T
O03
/INT
P4
P64
/RD
P65
/WR
0P
66/W
R1
P67
/AS
TB
P77
/EX
23/K
R7/
INT
P11
P76
/EX
22/K
R6/
INT
P10
P75
/EX
21/K
R5/
INT
P9
P74
/EX
20/K
R4/
INT
P8
P73
/EX
19/K
R3
P72
/EX
18/K
R2
P71
/EX
17/K
R1
P70
/EX
16/K
R0
P06
/WA
ITP
05/C
LKO
UT
EV
SS
1
P80
/EX
0P
81/E
X1
P82
/EX
2P
83/E
X3
P84
/EX
4P
85/E
X5
P86
/EX
6
P142/SCK20/SCL20P141/PCLBUZ1/INTP7P140/PCLBUZ0/INTP6
P120/INTP0/EXLVIP47/INTP2
P46/INTP1/TI05/TO05P45/SO01P44/SI01
P43/SCK01P42/TI04/TO04
P41/TOOL1P40/TOOL0
RESETP124/XT2P123/XT1
FLMD0P122/X2/EXCLK
P121/X1REGC
VSSEVSS0
VDDEVDD0
P60/SCL0P61/SDA0
75747372717069686766656463626160595857565554535251
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Cautions 1. Make AVSS the same potential as EVSS0, EVSS1, and VSS.
2. Make EVDD0 and EVDD1 the same potential as VDD. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remark When using the microcontroller for an application where the noise generated inside the microcontroller
must be reduced, it is recommended to supply separate powers to the two EVDD pins and connect the
two EVSS pins to separate ground lines.
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CHAPTER 1 OUTLINE
Users Manual U17894EJ6V0UD 21
Pin Identification
ANI0 to ANI15: Analog input
ANO0, ANO1: Analog output
ASTB: Address strobe
AVREF0, AVREF1: Analog reference voltage
AVSS : Analog ground
CLKOUT: Clock output
EVDD0, EVDD1: Power supply for port
EVSS0, EVSS1: Ground for port
EX0 to EX31: External extension bus
EXCLK: External clock input
(main system clock)
EXLVI: External potential input
for low-voltage detector
FLMD0: Flash programming mode
INTP0 to INTP11: External interrupt input
KR0 to KR7: Key return
P00 to P06: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30, P31: Port 3
P40 to P47: Port 4
P50 to P57: Port 5
P60 to P67: Port 6
P70 to P77: Port 7
P80 to P87: Port 8
P110, P111: Port 11
P120 to P124: Port 12
P130, P131: Port 13
P140 to P145: Port 14
P150 to P157: Port 15
PCLBUZ0, PCLBUZ1: Programmable clock output/
buzzer output
RD: Read strobe
REGC: Regulator capacitance
RESET: Reset
RTC1HZ: Real-time counter correction clock
(1 Hz) output
RTCCL: Real-time counter clock (32 kHz
original oscillation) output
RTCDIV: Real-time counter clock (32 kHz
divided frequency) output
RxD0 to RxD3: Receive data
SCK00, SCK01,
SCK10, SCK20: Serial clock input/output
SCL0, SCL10, SCL20: Serial clock input/output
SDA0, SDA10, SDA20: Serial data input/output
SI00, SI01,
SI10, SI20: Serial data input
SO00, SO01,
SO10, SO20: Serial data output
TI00 to TI07: Timer input
TO00 to TO07: Timer output
TOOL0: Data input/output for tool
TOOL1: Clock output for tool
TxD0 to TxD3: Transmit data
VDD: Power supply
VSS: Ground
WAIT: Wait
WR0: Lower byte write strobe
WR1: Upper byte write strobe
X1, X2: Crystal oscillator (main system
clock)
XT1, XT2: Crystal oscillator (subsystem clock)
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CHAPTER 1 OUTLINE
Users Manual U17894EJ6V0UD 22
1.5 78K0R Microcontroller Lineup
78K0R/KE3 78K0R/KF3 78K0R/KG3 78K0R/KH3 78K0R/KJ3 ROM RAM
64 Pins 80 Pins 100 Pins 128 Pins 144 Pins
512 KB 30 KB PD78F1168Note PD78F1178Note PD78F1188Note
384 KB 24 KB PD78F1167Note PD78F1177Note PD78F1187Note
256 KB 12 KB PD78F1146 PD78F1156 PD78F1166 PD78F1176Note PD78F1186Note
192 KB 10 KB PD78F1145 PD78F1155 PD78F1165 PD78F1175Note PD78F1185Note
128 KB 8 KB PD78F1144 PD78F1154 PD78F1164 PD78F1174Note PD78F1184Note
96 KB 6 KB PD78F1143 PD78F1153 PD78F1163
64 KB 4 KB PD78F1142 PD78F1152 PD78F1162
Note Under development
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CHAPTER 1 OUTLINE
Users Manual U17894EJ6V0UD 23
1.6 Block Diagram
Port 0 P00 to P067
Port 1 P10 to P17
Port 2 P20 to P278
Port 3 P30, P312
Port 4
Port 5
VSS,EVSS0,EVSS1
FLMD0 VDD,EVDD0,EVDD1
8
Port 6 P60 to P678
Port 7 P70 to P77
Port 12P121 to P124
Port 13P130
8
P40 to P478
P50 to P578
Port 14 P140 to P1456
Buzzer output
PCLBUZ0/P140, PCLBUZ1/P141
Clock output control
Voltage regulator REGC
Interrupt control
RAM
78K/0RCPUcore
Flash memory
Window watchdog timer
Internal low-speed oscillator
Power on clear/low voltage indicator
POC/LVIcontrol
Reset control
Key return 8 KR0/P70 to KR7/P77
EXLVI/P120
System control
RESETX1/P121X2/EXCLK/P122
Internal high-speed
oscillator
XT1/P123XT2/P124
Multiplier
On-chip debugTOOL0/P40TOOL1/P41
Real-time counter
Direct memoryaccess control
Serial array unit 0 (4 ch)
UART0
Serial array unit 1 (4 ch)
UART3
LINSEL
UART1
CSI00
IIC1
RxD0/P11TxD0/P12
RxD1/P03TxD1/P02
SCK00/P10
SO00/P12SI00/P11
SCL10/P04SDA10/P03
RxD3/P14TxD3/P13
Timer array unit (8 ch)
Ch 0
Ch 1
TI00/P00TO00/P01
TI01/TO01/P16
Ch 2TI02/TO02/P17
Ch 3TI03/TO03/P31
Ch 4TI04/TO04/P42
Ch 5TI05/TO05/P46
Ch 6TI06/TO06/P131
Ch 7
INTP1/P46,INTP2/P47
2
INTP0/P120
INTP5/P16
INTP8/P74 to INTP11/P77
4
INTP3/P30,INTP4/P31
2
INTP6/P140,INTP7/P141
2
RxD3/P14 (LINSEL)
CSI10SCK10/P04
SO10/P02SI10/P03
RxD3/P14 (LINSEL)
Serial interface IIC0SDA0/P61SCL0/P60
A/D converter
8ANI0/P20 to ANI7/P27
AVREF0AVSS
4
P120
2
Port 8 P80 to P878
Port 11 P110, P1112
P131
Port 15 P150 to P1578
D/A converter
ANO0/P110,ANO1/P111 AVREF1AVSS
2
8ANI8/P150 to ANI15/P157
External extention
EX0/P80 toEX7/P87
EX8/P50 toEX15/P57
EX16/P70 toEX23/P77
CSI01SCK01/P43
SO01/P45SI01/P44
IIC2SCL20/P142SDA20/P143
CSI20SCK20/P142
SO20/P144SI20/P143
8
8
EX24/P10 toEX31/P17
RxD2/P143TxD2/P144
UART2
RTC1HZ/P30
RTCDIV/RTCCL/P15
TI07/TO07/P145
BCDadjustment
8
8
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CHAPTER 1 OUTLINE
Users Manual U17894EJ6V0UD 24
1.7 Outline of Functions (1/2)
Item PD78F1162 PD78F1163 PD78F1164 PD78F1165 PD78F1166 PD78F1167 Note
PD78F1168Note
Flash memory
(self-programming
supported)
64 KB 96 KB 128 KB 192 KB 256 KB 384 KB 512 KB Internal
memory
RAM 4 KB 6 KB 8 KB 10 KB 12 KB 24 KB 30 KB
Memory space 1 MB
External memory expansion space 888 KB
max.
824 KB max. 760 KB
max.
696 KB
max.
568 KB
max.
440 KB
max.
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
2 to 20 MHz: VDD = 2.7 to 5.5 V, 2 to 5 MHz: VDD = 1.8 to 5.5 V
Main system
clock
(Oscillation
frequency) Internal high-speed
oscillation clock
Internal oscillation
8 MHz (TYP.): VDD = 1.8 to 5.5 V
Subsystem clock
(Oscillation frequency)
XT1 (crystal) oscillation
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Internal low-speed oscillation clock
(For WDT)
Internal oscillation
240 kHz (TYP.): VDD = 1.8 to 5.5 V
General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
0.125 s (Internal high-speed oscillation clock: fIH = 8 MHz (TYP.) operation)
Minimum instruction execution time
61 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set 8-bit operation, 16-bit operation Multiply (16 bits 16 bits) Bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total: 88
CMOS I/O: 79
CMOS input: 4
CMOS output: 1
N-ch open-drain I/O (6 V tolerance): 4
Timer 16-bit timer: 8 channels Watchdog timer: 1 channel Real-time counter: 1 channel
Timer outputs 8 (PWM output: 7)
RTC outputs 2 1 Hz (Subsystem clock: fSUB = 32.768 kHz) 512 Hz or 16.384 kHz or 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz)
Clock output/buzzer output 2 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (peripheral hardware clock: fMAIN = 20 MHz operation) 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation)
A/D converter 10-bit resolution 16 channels (AVREF0 = 2.3 to 5.5 V)
D/A converter 8-bit resolution 2 channels (AVREF1 = 1.8 to 5.5 V)
Note Under development
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CHAPTER 1 OUTLINE
Users Manual U17894EJ6V0UD 25
(2/2)
Item PD78F1162 PD78F1163 PD78F1164 PD78F1165 PD78F1166 PD78F1167Note 1
PD78F1168Note 1
Serial interface UART supporting LIN-bus: 1 channel CSI: 2 channels/UART: 1 channel CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel I2C bus: 1 channel
Multiplier 16 bits 16 bits = 32 bits
DMA controller 2 channels
Internal 28 Vectored interrupt
sources External 13
Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of the key input pins (KR0 to KR7).
Reset Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-clear Internal reset by low-voltage detector Internal reset by illegal instruction executionNote 2
On-chip debug function Provided
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = 40 to +85C
Package 100-pin plastic LQFP (14 20) (0.65 mm pitch) 100-pin plastic LQFP (14 14) (0.5 mm pitch)
Notes 1. Under development
2. When instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.
-
Users Manual U17894EJ6V0UD 26
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are five types of pin I/O buffer power supplies: AVREF0, AVREF1, EVDD0, EVDD1, and VDD. The relationship
between these power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF0 P20 to P27, P150 to P157
AVREF1 P110, P111
EVDD0, EVDD1 Port pins other than P20 to P27, P110, P111, P121
to P124, and P150 to P157
VDD P121 to P124 Pins other than port pins
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CHAPTER 2 PIN FUNCTIONS
Users Manual U17894EJ6V0UD 27
(1) Port functions (1/2)
Function Name I/O Function After Reset Alternate Function
P00 TI00
P01 TO00
P02 SO10/TxD1
P03 SI10/RxD1/SDA10
P04 SCK10/SCL10
P05 CLKOUT
P06
I/O Port 0.
7-bit I/O port.
Input of P03 and P04 can be set to TTL input buffer.
Output of P02 to P04 can be set to N-ch open-drain output
(VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
WAIT
P10 SCK00/EX24
P11 SI00/RxD0/EX25
P12 SO00/TxD0/EX26
P13 TxD3/EX27
P14 RxD3/EX28
P15 RTCDIV/RTCCL/EX29
P16 TI01/TO01/INTP5/
EX30
P17
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI02/TO02/EX31
P20 to P27 I/O Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Digital input
port
ANI0 to ANI7
P30 RTC1HZ/INTP3
P31
I/O Port 3.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI03/TO03/INTP4
P40Note TOOL0
P41 TOOL1
P42 TI04/TO04
P43 SCK01
P44 SI01
P45 SO01
P46 INTP1/TI05/TO05
P47
I/O Port 4.
8-bit I/O port.
Input of P43 and P44 can be set to TTL input buffer.
Output of P43 and P45 can be set to N-ch open-drain output
(VDD tolerance).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP2
P50 to P57 I/O Port 5.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port EX8 to EX15
Note If on-chip debugging is enabled by using an option byte, be sure to pull up the P40/TOOL0 pin externally
(see Caution in 2.2.5 P40 to P47 (port 4)).
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CHAPTER 2 PIN FUNCTIONS
Users Manual U17894EJ6V0UD 28
(1) Port functions (2/2)
Function Name I/O Function After Reset Alternate Function
P60 SCL0
P61 SDA0
P62
P63
P64 RD
P65 WR0
P66 WR1
P67
I/O Port 6.
8-bit I/O port.
Output of P60 to P63 can be set to N-ch open-drain output (6
V tolerance).
Input/output can be specified in 1-bit units.
For only P64 to P67, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
ASTB
P70 to P73 KR0/EX16 to KR3/
EX19
P74 to P77
I/O Port 7.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
KR4/EX20/INTP8 to
KR7/EX23/INTP11
P80 to P87 I/O Port 8.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port EX0 to EX7
P110 ANO0
P111
I/O Port 11.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Input port
ANO1
P120 I/O INTP0/EXLVI
P121 X1
P122 X2/EXCLK
P123 XT1
P124
Input
Port 12.
1-bit I/O port and 4-bit input port.
For only P120, use of an on-chip pull-up resistor can be