6645530 Allen and Holberg Homework Solution(2)
-
Upload
nihit-varshney -
Category
Documents
-
view
183 -
download
11
Transcript of 6645530 Allen and Holberg Homework Solution(2)
1
ECE 6412 - Spring 2006 Prof. Ayazi
EXAMINATION NO. 2 SOLUTIONS Problem 1 - (35 points) The op amps below have identical DC currents and W/L values for transistors with the same number. Find parametric expressions for entries in the table in terms of bias currents I5 and I7, Kn’, Kp’, λN, λP, VTN, |VTP|, S=W/L ratios, VDD, VSS, Cc, CL, and identify which is larger in magnitude for the two circuits. Assume K’n>K’p, VTN= -VTP, λN<λP, (W/L) 1= (W/L)2, VDD=-VSS. The threshold voltage is larger than the ON (saturation) voltage. Ignore body effect.
USE THE LAST SHEET TO DO YOUR WORK AND THEN WRITE YOUR FINAL ANSWER/EXPRESSION IN THE TABLE. NO PARTIAL CREDIT.
N-channel Input Op Amp P-channel Input Op Amp
Characteristic N-channel Input Op Amp <,=,> P-channel Input Op Amp
Small-signal output
resistance
17 6 7( ( ))I λ λ −+ = 1
7 6 7( ( ))I λ λ −+
Small-signal voltage gain 1 6
5 7 2 4 6 7
8( )( )
N PK K S SI I λ λ λ λ
′ ′
+ +
= 1 6
5 7 2 4 6 7
8( )( )
N PK K S SI I λ λ λ λ
′ ′
+ +
Gain-bandwidth 1 5N
c
K S IC′
>
1 5P
c
K S IC′
Upper input common
mode voltage
5
3DD TP TN
P
IV V VK S
− + −′
>
5 5
5 1
2DD TP
P P
I IV VK S K S
− − −′ ′
Slew rate(due to Cc)
5
c
IC
= 5
c
IC
Positive (VDD) PSRR
no expression needed < no expression needed
2
Negative (VSS) PSRR
no expression needed > no expression needed
Phase Margin
(EXTRA CREDIT)
1 5 1 51 1
6 7 6 7
90 tan ( ) tan ( )2 2
N NL
CP P
K S I K S ICCK S I K S I
− −′ ′− −
′ ′o
< 1 5 1 51 1
6 7 6 7
90 tan ( ) tan ( )2 2
P PL
CN N
K S I K S ICCK S I K S I
− −′ ′− −
′ ′o
3
Problem 2 - (35 points) The device parameters for the operational amplifier shown below are given in the table. Ignore the body effect of the MOS transistor and the internal capacitances of all the transistors. a. What resistance R in the emitter of Q9 is required to set the first stage bias currents in
the emitters of Q3 and Q4 at 10µA each? b. Calculate the overall voltage gain of the amplifier, by calculating the effective
transconductances of the differential input stage and the 2nd gain stage, and their effective output resistances.
c. Calculate the value of the miller capacitance Cc required to obtain a gain-bandwidth of 2MHz for this op-amp.
d. Calculate the phase margin of this op-amp.
a) RIC9=Vtln(IC8/IC9)
IC8=(20V-1.4V)/50kΩ=0.372mA IC9=20µA R=3.65kΩ
b) 61 13
1 3 3 1
1 1200 10 :1 2
m mmI e
m e m m
g g AG note that rg r V g g
−= = = × = =+
07 04 4 2 07 04
07 047 4
|| (1 ) || 2 5.65
: 13 5
I m e
Anpn Apnp
C C
R r r g r r r MV V
because r M and r MI I
= + × = = Ω
= = Ω = = Ω
1130vI mI IA G R= × =
103 13 13
13ln( ) 100C
C t CC
IR I V I A
Iµ= ⇒ =
31
1 2
31 1 10.663 10
1: 2 ( ) 1.414 10mm
mIImm
oxmm mm mmg AGg R V
W Anote that g C IL V
µ− −= = ×+
= = ×
1 1 2 013 13 3(1 ) || (1 ) 2.13 ||1.16 0.749II dsm mm mR r g R r g R M M M= + × + × = Ω Ω = Ω
497561,610
vII mII II
v vI vII
A G RA A A
= == × ≅
Parameter NPN PNP Beta 200 50 Early voltage 130V 50V VBE(on) 0.7V 0.7V Vt 25mV MOS lambda 0.01V-1 µCox 100µA/V2 VTO 0.7V
4
c) 6
6
200 10 15.92 2 10
mIC
C
GGBW C pFC π
−
−
×= ⇒ = =
× ×
d) ΦM = 90o − tan−1(
2MHzp2
) − tan−1(2MHz
z)
36
2 12
0.663 10 132 10 21.1sec5 10mII
L
G radp MHzC
−
−
×= = = × =
×
36
12
0.663 10 41.69 10 6.64sec15.9 10mII
C
G radz MHzC
−
−
×= = = × =
×
1 12 290 tan ( ) tan ( ) 90 5.41 16.76 67.8221 6.64M
− −⇒ Φ = − − = − − =o o o o o
5
Problem 3 - (30 points) In this problem, you are not asked to provide any numerical calculations. You are only required to provide expressions. Make sure that your final expression for each section is clearly identified and legible. For the cascoded two-stage CMOS Op-Amp shown below:
VSS
M3
M5
M6
M8
M4
M7
M9
M1 M2
VBP
VBN
V− V+
VOUT
VDD
CC
CL
31
2
4
VBIAS
a. Show an expression for the overall voltage gain of this amplifier as a function of transistor transconductances and output resistances.
1 4 2 6 7 6 7 8 8 9( || ) [( ) || ( )]II
v m ds ds m m ds ds m ds ds
R
A g r r g g r r g r r= ×14444244443
b. Show the expressions for the poles associated with the two capacitors CC and CL, as a function of the two capacitance values, transistor transconductances and output resistances. Assume that CC and CL include the transistor internal capacitances at their respective nodes.
1 24 2
1 1( || )ds ds c II L
p and pr r C R C
= =
c. If CL>>CC, provide an expression for the unity gain frequency (GB) of the amplifier.
1 6 4 2( || )m m ds ds
L
g g r rGBWC
=
6
d. Show an expression for the pole associated with node 3, in terms of transistors internal capacitances, transconductances and output resistances. Identify all the components of the internal capacitances.
36 3 3
3 7 7 6 6
7 8 8 9 8 8 93
7 7 7 7 7
1( || )
11
ds
gs sb gd db
ds m ds ds m ds ds
m ds m m ds
pr R C
C C C C C
r g r r g r rRg r g g r
=
= + + +
+= ≅ +
+
e. Is there a right half plane zero in this amplifier that would affect the phase margin? If there is, provide an expression for the position of this zero.
No, because a miller configuration is not used there is no RHZ that would affect the phase margin
f. (EXTRA CREDIT) Show expressions for any pole or zero associated with node 4. Identify all the components of the internal capacitances.
34
3 4 3 1 1
34
2
m
x
x gs gs db db gd
m
x
gpC
C C C C C C
gzC
−=
= + + + +
−=
ECE 6412- Spring 2006 Page 1
Homework No. 1 - Solutions
Problem 1 - (10 points)
A top view of a MOS transistor isshown. (a) Identify the type oftransistor (NMOS or PMOS) and itsvalue of W and L.
(b.) Draw the cross-section A-A’approxi- mately to scale.
(c) Assume that dc voltage of terminal 1is 5V, terminal 2 is 3V and terminal 3 is0V. Find the numerical value of thecapacitance between terminals 1 and 2, 2and 3, and 1 and 3. Assume that the dcvalue of the output voltage is 2.5V andthat the voltage dependence for pnjunction capacitances is for bothtransistors is -0.5 (this is called MJ inSPICE).
Solution
(a.) This transistor is an NMOStransistor with the drain as terminal 1, thegate as terminal 2, and the bulk andsource connected together to terminal 3.The W = 26µm and L = 4µm .
(b.) The approximate cross-section isshown (vertical scale is magnified by 4times).
(c.)With VDS = 5V, VGS = 3V and VT =0.75V, the transistor is in saturation.Therefore, the capacitors are:
C12 = CGD = LD(NMOS)xWxCox
= 0.45µm·26µm·0.7fF/µm2 = 8.19fF
C23 = CGS = LD(NMOS)xWxCox + 0.67(WxL)X Cox = 8.19fF + 48.776fF
= 56.966fF
C13 requires the area of the drain (AD) and the perimeter of the drain (PD). These values
are AD = 26µmx10µm = 260µm2 and PD = 2(10+26) = 72µm.
C13 = CBD = [AD·0.33fF/µm2+PD·0.9fF/µm]
1 + 5
0.6
= [260µm2 ·0.33fF/µm2+72µm·0.9fF/µm]
1 + 5
0.6
= 49.29fF
n+
p+
Metal
Poly
p-well
n-substrate
S00PES1
3
2 1
A A'
p-wellF
OX
p+
n+ n+
1µm
IOX
IOX
IOX
F
OX
ECE 6412- Spring 2006 Page 2
Problem 2 - (10 points)
Find the numerical values of I1, I2,VD, VE, and VC towithin ±5% accuracy.
Solution
First find I1. This is done by solving the equations I1 =K’W2L (VGS4-VT)2
and 5V = I1100kΩ + VGS4
Solving quadratically gives
VGS42 - VGS4
2 V T -
112 +
V T
2 - 512 = 0
VGS2 - 1.41667VGS + 0.145833 = 0
This gives VGS = 0.708335 ± 0.5965 = 1.305V ∴ VD = -2.5+1.305 = -1.195V
This value of VGS gives I1 = 5-1.195
100kΩ = 36.95µA
Neglecting the lambda effects, let I2 = 5I1 = 184.75µA
The base-emitter voltage of Q1 is found as
VE = -VBE1 = -VTln
I2
Is = -0.026ln
184.75µA
10fA = -0.614V
Finally, the value of VGS2 = 2I2
K’W2/L2 + VT = 2x184.75
800 + 0.75 = 1.43V
∴ VC = 2.5V - 1.43V = +1.070V
I1I2
1µm
50µm1µm
10µm1µm
M2
Q1
M3 M4
VC
VE VD
100kΩ
+2.5V
-2.5VS00PEP1
100µm
ECE 6412- Spring 2006 Page 3
Problem 3
Find the numerical values of all roots and themidband gain of the transfer function vout/vin of thedifferential amplifier shown. Assume that KN’ =
100µA/V2, VTN = 0.7V, and λN = 0.04V-1. Thevalues of Cgs = 0.2pF and Cgd = 20fF.
Solution
A small-signal model appropriate for this circuit isshown.
vin2
CgsCgd
gm1vgs1 rds1RL CL
vout2
+
-Fig. S03E1S4
Summing the currents at the output nodes gives,
gm1vgs1 + sCgd(vout-vin) + (gds1 + GL)vout + sCL vout = 0
(Note: we are ignoring the fact that vout and vin should be divided by two since it makes nodifference in the results and is easier to write.) Replacing vgs1 by vin gives
-(gm1 - sCgd)vin = [(gds1 + GL) + sCL + sCgd] vout
voutvin
= -(gm1 - sCgd)
s(CL + Cgd) + (gds1 + GL) =
-gm1
gds1 + GL
1 -
sCg dgm
1 + s C L + C gd gds1 + GL
∴ MGB = - gm1(rds||RL), Zero = gmCgd
and Pole = - gds + GLCgd + CL
gm = 2·100·100·500 = 3162.3µS and rds = 1
λID =
25500µA = 50 kΩ
∴ MGB = -3.162mS·(10kΩ||50kΩ) = -26.35 V/V
Zero = 3.162x10-3
20x10-15 = 1.581x10 11 radians/sec.
Pole = -1
1.02x10-12(10kΩ||50kΩ) = -1.1176x10 8 radians/sec.
RL=10kΩ
100/1100/1M1 M2
1mA
VDD
S03E1P4
+- voutCL =1pF CL =1pF
vin
RL=10kΩ
ECE 6412- Spring 2006 Page 4
Problem 4
Find the voltage transfer function of the common-gate amplifiershown. Identify the numerical values of the small-signal voltagegain, vout/vin, and the poles and zeros. Assume that ID =250µA, KN’ = 100µA/V2, VTN = 0.5, λ ≈ 0V-1, Cgs = 0.5pF and Cgd = 0.1pF.
Solution
The small signal transconductance is,
gm = 2·KN·(W/L)ID = 2·100·20·250 = 1mS
rds = ∞
The small signalmodel is,
The voltage gain can be expressed as follows,
VoutVin
=
Vout
Vgs
Vgs
Vin ,
VoutVgs
= -gm
RL(1/sCgd)
RL+(1/sCgd)
Sum currents at the source to get,
Vin + Vg sRs
+ gmVgs + sCgsVgs = 0 →VgsVin
= -Gs
Gs + gm + sC g s
∴VoutVin
=
gmRL
1+ gmRL
1
sCgdRL+1
1
sCgsgm+Gs
+ 1
The various values are,
Voltage gain = gmRL
1+ gmRL =
1·101+1 = 5V/V
p1 = -1
CgdRL =
-1
10-13·104 = -10 9 radians/sec.
p2 = -(gm+Gs)
Cgs =
-10-3+10-3
0.5x10-12 = -4x10 9 radians/sec.
VDD
VBias
RD =10kΩ
vout
+
-RS =1kΩ
vin
201
S04E1P3
ID
vin vgs
+
-
Cgs
Rsgmvgs
CgdRL
vout
+
-S04E1S3
ECE 6412- Spring 2006 Page 5
Problem 5
Draw the electrical schematic using the proper symbols for the transistors. Identify on your
schematic the terminals which are +5V, ground, input, and output. Label the transistors on
the layout as M1, M2, etc. and determine their W/L values. Assume each square in the
layout is 1 micron by 1 micron. Find the area in square microns and periphery in microns
for the source and drain of each transistor.
D1
G1 B1
S1
S2G2
D2
B2
OutputInput
= 10
W2L2
= 20
AS1 = AD1 = 40x8 = 320µm2PS1 = PD1 = 8+8+40+40 = 48µm
AS2 = 2AS1 = 640 µm2
AD2 = AD1 = 320µm2
PS2 = 2PS1 =192µmPD2 = PD1 = 96µm
S01PES1
Metal + p-well Poly Contact
N-Substrate
+5VInput
Output
Ground
pn+
+5Volts
Ground
M1
M2
M1
M2
W1L1
ECE 6412 - Spring 2006 Page 1
Homework Assignment No. 4 - Solutions
Problem 1
Find the midband voltage gain and the –3dB frequency in Hertz for the circuit shown.
-
+Vin Vout
R1=1kΩ
R2=10kΩ
C1=10pF
C2=1pF
V1
100-
+V1
R3=20kΩ
C3=10pF
S02E1P3Solution
The midband gain is given as,
VoutVin
= -
20kΩ
100
10kΩ
11kΩ = -181.82V/V
To find the –3dB frequency requires finding the 3 open-circuit time constants.
RC10:
RC10 = 1kΩ||10kΩ = 0.9091kΩ → RC10C = 0.9091x10ns =9.09nsRC20:
vt = it RC10 + R3(it+0.01V1)
= it(RC10 + R3 + 0.01RC10R3)
∴ RC20 = RC10 + R3 + 0.01RC10R3
=0.9091+20x(1+0.01·909.1)kΩ = 202.72kΩ
RC20C2 = 202.72x1ns =202.72ns
RC30:
RC30 = 20kΩ → RC30C3 = 20x10ns = 200ns
ΣT0 = (9.091 + 202.72 + 200)ns=411.82n → ω-3dB = 1
ΣT0 = 2.43x106 rad/s
f-3dB = 2.43x106
2π = 386.5kHz
R3Rc10
it
vt+ -
+
-V1 V1
100
S02E1S3
ECE 6412 - Spring 2006 Page 2
Problem 2 – (10 points)
Find the midband voltage gain and the exact value of the two poles of the voltage transferfunction for the circuit shown. Assume that RI = 3kΩ, RL = 9KΩ, gm = 1mS, Cgs = 4.5pFand Cgd = 1pF. Ignore rds.
-
+Vin Vout
RI
RL
S02E1P4
Solution
The best approach to this problem is a direct analysis.
Small-signal model:
-
+
Vin VoutCgs
RIgmVgs
Vgs Cgd RL
-
+
-
+Vin VoutCgs
RI
Vs Cgd RL
-
+
gmVs
S02E1S4
Vout = gmZLVs where ZL = 1
sRLCgd+1 and Vin-Vs
RI = gmVs +
sCgsVs
Solving for Vs from the second equation gives,
Vs = Vin
1+gmRI +sCgsRI
Substituting Vs in the first equation gives,
Vout = gmZL
Vin1+gmRI +sCgsRI
→ VoutVin
= gm
1
sRLCgd+1
1
1+gmRI +sCgsRI
=
gmRL
1+gmRI
1
sRLCgd+1
1
sCgdRI1+gmRI
+ 1 = MBG
1
1 - s
p1
1
1 - sp2
∴ MBG =
gmRL
1+gmRI =
1x9
1+1x3 = 2.25V/V
p1 = -1
RLCgd = -
19x1ns = 1.1e8 10 rad/s and p2 =-
1+gmRIRICgs
= - 1+3
3x4.5ns = -2.9x10 8 rad/s
ECE 6412 - Spring 2005 Page 1
Homework Assignment No. 6 - Solutions
Problem 1 - (10 points)
For the CMOS op ampshown, find the followingquantities.
1.) Slew rate (V/sec.)
2.) Positive and negativeoutput voltage limits (alltransistors remain insaturation)
3.) Positive and negativeinput common voltage limits(all transistors remain insaturation and use nominalparameter values)
4.) Small signal voltage gain
5.) Unity-gainbandwidth (MHz) and 6.) Power dissipation (mW).
Solution
1.) SR = I5Cc
= 40µA3pF = 1.1x107V/second ⇒ SR =1.1x107V/sec
2.) VSD7 = 2I7
KP(W/L) = 480µA50·60 = 0.4V and VDS6 =
480µA110·60 = 0.2697V
∴ Vout(max) = 2.5-0.4 = 2.1V &
Vout(min) = -2.5V+0.2697V = -2.230V
3.) ICM (min) = -2.5V+VGS3 -|VTP| = -2.5V+2·20
110·10 +0.7V-0.7V
∴ ICM(min) = -2.5+0.191 = -2.309V ⇒ ICM(min) = -2.309V
ICM(max) = ? VSD5(sat) = 2·4050·10 = 0.4V and VSG1 =
2·2050·10 + 0.7 = 0.983V
∴ ICM(max) = 2.5 -VSD5(sat) -VSG1 = 2.5-0.4-0.983 = 1.117V ICM(max) = 1.1171V
4.) Av = gm1gm6
(gsd2+gds4)(gds6+gsd7) gm1 = 2KPW1I1
L1 = 2·50·10·20 = 141µS
gm6 = 2KPW6I6
L6 = 2·110·60·240 = 1779µS GI = 0.09·20µA = 1.8µS
and GII = 0.09·240µA = 21.6µS
∴ Av = 141x17791.8x21.6 = 6,452V Av = 6,452V/V
5.) GB = gm1Cc
= 141µS
3pF = 47Mrads/sec ⇒ GB = 7.48MHz
6.) Pdiss = 5x320µA = 1.6mW ⇒ Pdiss = 1.6mW
-
+vin M1 M2
M3 M4
M5 M7
M6
vout
VSS=-2.5V
Cc=3pFM8
10/1
10/1 10/1
10/1 10/1
60/110/1
60/1
VDD=2.5V
40µA
S99E2P4
ECE 6412 - Spring 2005 Page 2
Problem 2 - (10 points)
Bias current calculation:
ssddSONT VVRIVV −=++ .888 or, s
p
T RIK
IV .5
.3
.28/
88 −=+ . (1)
Solving for 8I quadratically would give, I8 __ 36µA , I5 __ 36µA , and I7 __ 60µA
Using the formula, IL
WKgm ..2 /= and Igds λ= we get,
Sgm µ602 = , Sgds µ9.02 = , Sgds µ72.04 = (2)
Sgm µ3636 = , Sgds µ36 = , Sgds µ4.27 = (3)
Small-signal open-loop gain:
The small-signal voltage gain can be expressed as,
37)( 42
21 −=
+
−=
dsds
mV
gg
gA and 67
)( 76
62 −=
+
−=
dsds
mV
gg
gA
Thus, total open-loop gain is,
Av = Av1·Av2 = 2489V/V (3)
Output resistance:
Ω=+
= Kgg
Rdsds
out 185)(
1
76(5)
Power dissipation:
WWPdiss µµ 660)603636(5 =++= (6)
ICMR:
VVVVV ONONTin 51.05.2 511max, =−−−= (7)
VVVVV ONTTin 21.25.2 331min, −=++−−= (8)
Output voltage swing:
VVV ON 81.15.2 7max,0 =−= (9)
Slew Rate:
Slew rate under no load condition can be given as,
sVC
ISR
C
µ/65 ==
In presence of a load capacitor of 20 pF, slew rate would be,
SR = min
I5
Cc,I7CL
ECE 6412 - Spring 2005 Page 3
Problem 6.3-7 - Continued
CMRR:
Under perfectly balanced condition where 21 II = , if a small signal common-mode
variation occurs at the two input terminals, the small signal currents 4321 iiii === and thedifferential output current at node (7) is zero. So, ideally, common-mode gain would bezero and the value for CMRR would be infinity.
GBW:
Let us design M9 and M10 first. Both these transistors would operate in triode region andwill carry zero dc current. Thus, 0109 ≅= dsds VV . The equation of drain current in trioderegion is given as,
( ) DSTGSD VVVL
WKI ./ −≅ .
The on resistance of the MOS transistor in triode region of operation would be,
( )TGSON VVL
WKR −= /
.
It is intended to make the effective resistance of M9 and M10 equal to 6
1
mg.
So, K’9
W9
L9 (VGS9-VT9) + K’10
W10
L10 (VGS10-VT10) = gm6 (11)
VVVVV ONTDD 51.15.2 3334 −=++−==
Thus, VVGS 49 ≅ and VVGS 110 −≅ .Putting the appropriate values in (11), we can solve for the aspect ratios of M9 and M10.One of the solutions could be,
K’9
W9
L9 =
11 and K’10
W10
L10 = very small (12)
The dominant pole could be calculated as,
=640HZ
( ).
... 224
1 CA
ggp
CV2
dsds +−=
π
And the load pole would be,
.8.2..2
62 MHz
C
gp
L
m −=−
=π for a 20 pF load.
It can be noted that in this problem, the product of the open-loop gain and thedominant pole is approximately equal to the load pole. Thus, the gain bandwidth isapproximately equal to 2.8 MHz and the phase margin would be close to 45 degrees.
ECE 6412 - Spring 2005 Page 4
Problem 6.3-7 - Continued
PSRR:If a small ripple Sv is applied at the ddV terminal, then the gain of this ripple from
this terminal to the output can be expressed as,
vovs
=
1-
RSRS+(1/gm8) gm7
gds6+gds7 = 2.8V/V
Thus, PSRR due to variations in ddV would be, 8898.2/24898.2 ==VA .
SPICE file:
.model nmos nmos vto=0.7 lambda=0.04 kp=110u
.model pmos pmos vto=-0.8 lambda=0.05 kp=50u
vdd 1 0 dc 2.5 ac 0vss 10 0 dc -2.5 ac 0vinp 5 0 dc 0 ac 1*vinn 4 0 dc 0 ac 0
m8 2 2 1 1 pmos w=3u l=1urs 2 10 100km5 3 2 1 1 pmos w=3u l=1um1 6 8 3 3 pmos w=2u l=1um2 7 5 3 3 pmos w=2u l=1um3 6 6 10 10 nmos w=4u l=1um4 7 6 10 10 nmos w=4u l=1um7 8 2 1 1 pmos w=5u l=1um6 8 7 10 10 nmos w=10u l=1ucc 7 9 6pcl 8 0 20pm9 8 1 9 9 nmos w=1u l=1um10 8 10 9 9 pmos w=1u l=100u
.op
.ac dec 10 1 100meg
.option post
.end
Operating points:
**** mosfets
subcktelement 0:m8 0:m5 0:m1 0:m2 0:m3 0:m4model 0:pmos 0:pmos 0:pmos 0:pmos 0:nmos 0:nmosregion Cutoff Cutoff Cutoff Cutoff Saturati Saturati id -35.3708u -34.8506u -17.4107u -17.4399u 17.4107u 17.4399u ibs 0. 0. 0. 0. 0. 0. ibd 14.6292f 11.4726f 28.7676f 28.3314f -9.7598f -10.1959f
ECE 6412 - Spring 2005 Page 5
Problem 6.3-7 - Continued
vgs -1.4629 -1.4629 -1.3517 -1.3527 975.9818m 975.9818m vds -1.4629 -1.1473 -2.8768 -2.8331 975.9818m 1.0196 vbs 0. 0. 0. 0. 0. 0. vth -800.0000m -800.0000m -800.0000m -800.0000m 700.0000m700.0000m vdsat -662.9217m -662.9217m -551.7476m -552.7377m 275.9818m275.9818m beta 160.9719u 158.6045u 114.3838u 114.1657u 457.1773u 457.9449u gam eff 527.6252m 527.6252m 527.6252m 527.6252m 527.6252m 527.6252m gm 106.7118u 105.1423u 63.1110u 63.1037u 126.1726u 126.3844u gds 1.6480u 1.6480u 761.0636n 763.7975n 670.2604n 670.2604n gmb 36.9704u 36.4266u 21.8648u 21.8623u 43.7126u 43.7860u cdtot 2.021e-18 1.585e-18 2.649e-18 2.609e-18 1.797e-18 1.878e-18 cgtot 7.005e-16 7.000e-16 4.693e-16 4.692e-16 9.467e-16 9.467e-16 cstot 6.906e-16 6.906e-16 4.604e-16 4.604e-16 9.208e-16 9.208e-16 cbtot 7.806e-18 7.806e-18 6.216e-18 6.205e-18 2.402e-17 2.402e-17 cgs 6.906e-16 6.906e-16 4.604e-16 4.604e-16 9.208e-16 9.208e-16 cgd 2.021e-18 1.585e-18 2.649e-18 2.609e-18 1.797e-18 1.878e-18
subcktelement 0:m7 0:m6 0:m9 0:m10model 0:pmos 0:nmos 0:nmos 0:pmosregion Cutoff Saturati Linear Cutoff id -61.7971u 61.7971u 0. 0. ibs 0. 0. 0. 0. ibd 24.9901f -25.0099f 0. 0. vgs -1.4629 1.0196 2.4990 -2.5010 vds -2.4990 2.5010 0. 0. vbs 0. 0. 0. 0. vth -800.0000m 700.0000m 700.0000m -800.0000m vdsat -662.9217m 319.5939m 0. 0. beta 281.2376u 1.2100m 110.0000u 500.0000n gam eff 527.6252m 527.6252m 527.6252m 527.6252m gm 186.4385u 386.7225u 0. 0. gds 2.7467u 2.2471u 197.8911u 850.4951n gmb 64.5917u 133.9802u 0. 0. cdtot 5.753e-18 1.152e-17 1.727e-16 17.2658f cgtot 1.1698f 2.3660f 3.463e-16 34.6349f cstot 1.1511f 2.3021f 1.727e-16 17.2658f cbtot 1.301e-17 5.233e-17 9.769e-19 1.033e-16 cgs 1.1511f 2.3021f 1.727e-16 17.2658f cgd 5.753e-18 1.152e-17 1.727e-16 17.2658f
Results from SPICE simulation:
i. Unloaded output (load capacitor = 0)
GBW = 1.5 MHz., Phase Margin = 90 deg, 1% settling time = 0.39 us.
ii. Loaded output (load capacitor = 20 pF)
GBW = 1.5 MHz., Phase Margin = 65 deg, 1% settling time = 0.48 us.
ECE 6412 - Spring 2005 Page 6
Problem 6.3-7 - Continued
ECE 6412 - Spring 2005 Page 7
Problem 6.3-7 - Continued
ECE 6412 - Spring 2005 Page 8
Problem 3 - (10 points)
Small signal differential voltage gain:
By intuitive analysis methods,vo1vin
= -0.5gm1
gds1 + gds3
and
voutvo1
= -gm4
gds4 + gds5
∴ voutvin
= 0.5gm1gm4
(gds1+gds3)(gds4+gds5)
gm1 = 2KNW1ID1
L1 = 24·2·4·10 x10-6 = 43.82µS
gds1 = λNID1 = 0.01·10µA = 0.1µS, gds3 = λPID3 = 0.02·10µA = 0.2µS
gm4 = 2KPW4ID4
L4 = 2·8·10·100 x10-6 = 126.5µS
gds4 = λPID4 = 0.02·100µA = 2µS, gds5 = λNID5 = 0.01·100µA = 1µS
∴ voutvin
= 0.5·43.82·126.5
(0.1+0.2)(1+2) = 3,079V/V
Output resistance:
R out = 1
gds4+gds5 =
106
1+2 = 333kΩ
Dominant pole, p1:
|p1| = 1
R1C1 where R1 =
1gds1+gds3
= 106
0.1+0.2 = 3.33MΩ
and
C1 = Cc(1+|Av2|) = 5pF
1 +
gm4gds4+gds5
= 5
1+
126.53 = 215.8pF
∴ |p1| = 106
3.33·2.15.8 = 1,391 rads/sec → |p1| = 1,391 rads/sec = 221Hz
GB = 0.5·gm1
Cc =
0.5·43.82x10-6
5x10-12 = 4.382Mrads/sec
GB = 4.382 Mrads/sec = 0.697MHz
SR = ID 6Cc
= 10µA
5pF = 2V/µs Pdiss = 10V(140µA) = 1.4mW
+
-vin
M1
M2
M5
M3vout
M4
M6M7
M8
10/1
5/11/11/1
2/1
20µA4/1
4/1
1/1
+5V
-5V
5pF
10µA
vo1
10µA100µA
ECE 6412 - Spring 2005 Page 9
Problem 4 - Des ign Problem 2 (50 points)
ECE 6412 - Spring 2006 Page 1
Homework Assignment No. 8 - Solutions
Problem 1 - (10 points)
This problem dealswith the op ampshown in Fig.P6.5-15. Alldevice lengths are1µm, the slew rateis ±8V/µs, the GBis 8MHz, themaximum outputvoltage is +2V, theminimum outputvoltage is -2V, andthe input commonmode range is from-1V to +2V.Design all W valuesof all transistors inthis op amp. Yourdesign must meet orexceed the specifications. When calculating the maximum or minimum output voltages,divide the voltage drop across series transistors equally. Ignore bulk effects in thisproblem. When you have completed your design, find the value of the small signaldifferential voltage gain, Avd = vout/vid, where vid = v1-v2 and the small signal outputresistance, Rout.
Solution
1.) The slew rate will specify I. ∴ I = C·SR = 10-11x8x106 = 10-4 = 80µA.
2.) Use GB to define W1 and W2.
GB = gm1C → gm1 = GB·C = 2πx8x106·10-11 = 502.4µS
∴ W1 = gm1
2
2KN(0.5I) = (502.4)2
2·110·40 = 28.68 ⇒ W 1 = W 2 = 29µm
3.) Design W15 to give VT+2VON bias for M6 and M7. VON = 0.5V will meet the desiredmaximum output voltage specification. Therefore,
VSG15 = VON15 + |VT| = 2(0.5V) + |VT| → VON15 = 1V = 2I
KPW15
∴ W15 = 2I
KPVON152 =
2·8050·12 = 3.2µm ⇒ W 15 = 4µm
4.) Design W3, W4, W6 and W7 to have a saturation voltage of 0.5V with 1.5I current.
W3 =W4 =W6 =W7 = 2(1.5I)
KPVON2 =
2·12050·0.52 = 19.2µm ⇒ W 3 = W 4 = W 6 = W 7 = 20µm
+3V
-3V
I
I
I
0.5I 0.5I
1.5I 1.5I
I I
I
vout
10pF
v1
v2
M1
M2
M3 M4
M5
M6 M7
M8 M9
M10 M11M12M13
M15
M14
Figure P6.5-15
ECE 6412 - Spring 2005 Page 2
Problem 6.5-15 – Continued
5.) Next design W8, W9, W10 and W11 to meet the minimum output voltage specification.Note that we have not taken advantage of smallest minimum output voltage because anormal cascode current mirror is used which has a minimum voltage across it of VT +2VON. Therefore, setting VT + 2VON = 1V gives VON = 0.15V. Using worst casecurrent, we choose 1.5I. Therefore,
W8 =W9 =W10 =W11 = 2(1.5I)
KNVON2 =
2·120110·0.152 = 96.8µm ⇒ W 8 = W 9 = W 10 = W 11 =
97µm
6.) Check the maximum ICM voltage.
Vic(max) = VDD + VSD3(sat) + VTN = 3V – 0.5 + 0.7 = 3.2V which exceeds spec.
7.) Use the minimum ICM voltage to design W5.
Vic(min) = VSS + VDS5(sat) + VGS1 = -3 + VDS5(sat) +
2·40
110·29+0.7 = -1V
∴ VDS5(sat) = 1.142 → W5 = 2I
KN VDS5(sat)2 = 1.11µm = 1.2µm
Also, let W12 =W13 =W5 ⇒ W 12 = W 13 = W 5 = 1.2µm
8.) W14 is designed as
W14 = W3
I14I3
= 20µm I
1.5I = 13.3µm ⇒ W 14 = 14µm
Now, calculate the op amp small-signal performance.Rout ≈ rds11gm9rds9||gm7rds7(rds2||rds4)
gm9 = 2KN·I·W9 = 1306µS, rds9 = rds11 = 25V
80µA = 0.312MΩ,
gm7 = 2KP·I·W7 = 400µS, rds7 = 20V
80µA = 0.25MΩ, rd2 = 25V40µA = 0.625MΩ
rds4 = 20V
120µA = 0.1667MΩ ∴ R out ≈ 127ΜΩ||13.16ΜΩ = 11.92ΜΩ
Avd=gm1 Routgm1 = KN·I·W1 = 505µS
∴ Avd = (505µS)(11.92MΩ) = 6,022V/V ⇒ A vd = 6,022V/V
ECE 6412 - Spring 2005 Page 5
Problem 5 – (10 points)
A two-stage, BiCMOS op amp is shown.For the PMOS transistors, the modelparameters are KP’=50µA/V2, VTP = -0.7V
and λP = 0.05V-1. For the NPN BJTs, the
model parameters are βF = 100, VCE(sat) =0.2V, VA = 25V, Vt = 26mV, Is = 10fA andn=1. (a.) Identify which input is positiveand which input is negative. (b.) Find thenumerical values of differential voltage gainmagnitude, |Av(0)|, GB (in Hertz), the slewrate, SR , and the location of the RHP zero.(c.) Find the numerical value of themaximum and minimum input commonmode voltages.
Solution
(a.) The plus and minus signs on the schematic show which input is positive and negative.
(b.) The differential voltage gain, Av(0), is given as
Av(0) = gm1
gds2+go4+gπ6 ·
gm6gds7+go6
gm1 = gm2 = 50·25·20 = 158.1µS
rds2 =1
λPID =
2012.5µA = 1.6MΩ,ro4=
VAIC
= 25V12.5µA2=MΩ, gm6 =
ICVt
= 50µA26mV =1923µS
rπ6 = βFgm6
= 52kΩ rds7 = 1
λPID =
2050µA = 0.4MΩ and ro6 =
VAIC
= 25V
50µA = 0.5MΩ
∴ |Av(0)| = [158.1(1.6||2||0.052)][1923(0.4||0.5)] = 3319.3V/V
GB = gm1Cc
= 158.1µS
5pF = 31.62x106 rads/sec → GB = 5.0325MHz
SR = 25µA5pF = 5V/µs
RHP zero = gm6Cc
= 1.923mS
5pF = 384.6x10 6 rads/sec =61MHz
(c.) The maximum input common mode voltage is given as
vicm+ = VCC-VDS5(sat) - VSG1 = 1.2 - 2·2550·20 - 0.7 -
2x12.550·20 = 0.5 - 0.224-0.158 =
∴ vicm+ = 0.118V
vicm- = -1.2 + VBE3 - VT1 = -1.2 + Vt ln
12.5µA
10fA - 0.7 = -1.9 + 0.545 = -1.3554V
v1
M8 M5 M7
vout
1.2V
-1.2V
Cc=5pF
v2
M1 M2
Q3 Q4
Q6
25µA
20/1 40/120/1
20/1 20/1
W/L ratiosin microns
S01E2P1
+-
50µA25µA
12.5µA
ECE 6412 - Spring 2006 Page 1
Homework Assignment No. 9 Solutions Problem 1 – (10 points)
Problem 2 – (10 points)
Problem 3 – (10 points)
Problem 4 – (10 points)
Problem 5 – (10 points)
Problem 6 – (10 points)
Problem 7 – (10 points)
Problem 8 – (10 points)
Problem 9– (10 points)
Problem 10– (10 points)
Homework Assignment No. 10 Solutions
Problem 4
Problem 6– P7.2-4 Use the technique of Ex. 7.2-2 to extend the GB of the cascode op amp of Ex. 6.5-2 as much as possible that will maintain 60° phase margin. What is the minimum value of CL for the maximum GB?
Solution
Assuming all channel lengths to be 1 mµ , the total capacitance at the source of M7 is 66777 bdgdbdgs CCCCC +++= or, 18651951757 =+++=C fF 7077 =mg Sµ Thus, the pole at the source of M7 is
605
7
77 !=!=
C
gp mS MHz.
The total capacitance at the source of M12 is 1111121212 bdgdbdgs CCCCC +++= or, 96294293412 =+++=C fF 70712 =mg Sµ Thus, the pole at the source of M12 is
1170
12
1212 !=!=
C
gp mS MHz.
The total capacitance at the drain of M4 is 224644 bdgdbdgsgs CCCCCC ++++= or, 1611932175434 =++++=C fF 2834 =mg Sµ
ECE 6412 - Spring 2006 Page 11
Problem 6 - Continued Thus, the pole at the drain of M4 is
280
4
44 !=!=
C
gp mD MHz.
The total capacitance at the drain of M8 is 1210888 gsgsbdgd CCCCC +++= or, 12834345198 =+++=C fF
4.31
10
2 =+mg
R !K
Thus, the pole at the drain of M8 is
!
pD8 = "1
R2+1
gm10
#
$ % &
' ( C
8
= "366 MHz.
For a phase margin of o60 , we have
!
PM =180o " 90o " tan
"1 GB
pS7
#
$ % &
' ( + tan"1
GB
pS12
#
$ % &
' ( + tan"1
GB
pD4
#
$ % &
' ( + tan"1
GB
pD8
#
$ % &
' (
) * +
, - .
/
0 1
2
3 4
Solving the above equation 65!GB MHz.
And, 6925=vA V/V Thus, 39.91 =p KHz, and
!
CL"1.54 pF
ECE 6412 - Spring 2006 Page 1
Homework Assignment No. 11 Solutions Problem 1 – (10 points)
Problem 2 – (10 points)
Common mode half circuit:
1 2 3
3'
1 2
1 1 3
' '1
'
3
' '
3 3
2 0.8
2.5 0.8 1.7
( 20 ) 1(100 200 20) 15.38, :
2 5000 0.2 1
2 2 1000.2
o o DD GS
DGS TP ov TP
p
o o
dm m o o
m n D n ov
pD
ov
p p
V V V V
IV V V V VwkL
V V V
a g r r K where
w wg k I k v mSL L
wkLIv
w wk kL L
µ
= = −
= + = + =
⇒ = = − =
= − = − = −
= = = × =
⎛ ⎞⎜
× ⎝= ⇒ = ⇒
⎛ ⎞ ⎛ ⎞⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
3
'
1
1 3
5000
5000
100 , 200
n
o o
wkL
r K r K
µ
µ
⎧=⎟⎪ ⎠⎪
⎨⎛ ⎞⎪ =⎜ ⎟⎪ ⎝ ⎠⎩
= =
11 1 5 3
1 5 3
3
5
1 1( (1 2 ) ) 0.01, :1 2 1 2 50
5000 0.2 150
mcm o m o o
m o m
m
o
ga r g r rg r g m K
g mSr K
= − + = =+ + ×
= × ==
where
Because of adding the 20Kresistors, the adm becomes smaller but acm becomes much smaller. The effective impedance of M3 and M4 is now 1/gm, which is much smaller than ro adm/acm=1538 which is much higher than 100 in 12.4.1
Problem 3 – (10 points)
Without Ccs:
11 2
1
1 2
11
1( )( )
1( )
212
( 1) 12
cs
cms ov ov
cs cs
ov ovoc
cms cscms
csoc cs cs cs
RC s
v v vR R
C sv vv
v R a R C sv R R R C s
= ++
+=
= ⇒ =+ + +
Gain starts to drop at frequencies higher than the pole. In Other words the CM detector cannot follow the signal at the same rate.
With Ccs:
11 2
1
1 2
11
1( )( )
( )1 1( ) ( )
( )
21 12
1 1 ( ) 1 ( )2
cscs
cms ov ov
cs cscs cs
ov ovoc
cms cs cs cs cscms
oc cs cs cs cscs cs
RC C s
v v vR R
C C s C sv vv
v R C s Ra Cv R C s R C s C sC s
R C s
+= +
++
+=
+ += ⇒ =
+ + + + + +
If 1
2csCC >> gain stays constant over the entire frequency range.
Problem 4 – (10 points)
12
12 12
11
51
51
51 51
14
( ) 20 ( ) 19.2 19.2100( )
120
( ) 120 16( ) 1.2 0.8 19.2 19.2100 0.8( )
D
wwL w mw L
LIw
wL w mw LL
µ
µ
µ
= ⇒ = ⇒ =
=
= ⇒ = × × = ⇒ =
100 25 sec4A VSR
pFµ
µ= =
1 min 51 1 1 1
1 max 27 24
max( 1.65 , )1.65
o ov ov ov C i
o ov gs
v v v v vv v v
= − + + + − += − −
t ov Cv v
Problem 5 – (10 points)
3 1
6 2
' '
6 '
3 '
0
1
21
126, 57
20 0.079(25)
20 0.083(50)
0.16( 3.5 0.65 0.65) 0.8972.5 1 0.083 1.41
2 1 60,126 (1.41 0.897)
o DD ds gs
o DD ds gs
n n ox p p ox
ovn
ovp
tn t
gs
v v v v
v v v v
k C k C
v Vk
v Vk
V V Vv V
w mA wL
µ µ
µ
µ
µ
+
−
= − −
= − −
= = = =
= =
= =
= + + − =⇒ = − − =
×⎛ ⎞⇒ = =⎜ ⎟ × −⎝ ⎠ 4
0
2
22 4
0.1 60 6
0.44( 3.5 0.65 0.65) 1.242
2.5 1 0.079 1.421
2 1 1095, 0.1 1095 109.557 (1.421 1.242)
tp t
gs
L
V V V
v V
w mA wL Lµ
⎛ ⎞ = × =⎜ ⎟⎝ ⎠
= − + − = −
⇒ = − + + =
×⎛ ⎞ ⎛ ⎞⇒ = = = × =⎜ ⎟ ⎜ ⎟× −⎝ ⎠ ⎝ ⎠
ECE 6412 - Spring 2006 Page 1
Homework Assignment No. 12 Solutions Problem 1 – (10 points)
Problem 2 – (10 points) Applying the half-circuit principle, it can be seen that each ½ circuit consists of a cascade of two common-source (CS) stages – the first with a diode connected PMOS load and the other with an NMOS load. The half circuit representation is shown along-side. The gain of the first stage is:
3
11
m
moutmv g
gRGA ==
In general for a CS stage with an active load, the primary noise contributors can be represented as shown below (for the second CS stage in the problem). From the figure along-side, we have:
( ) fWLCgKgkTi
OX
mPmn
5
25
52
5324 +⎟⎠⎞
⎜⎝⎛=
( ) fWLCgKgkTi
OX
mNmn
7
27
72
7324 +⎟⎠⎞
⎜⎝⎛=
Therefore the input referred noise at the gate of M5 is given by:
25
27
252
1
m
nno
giiv +
=
Similarly, the noise at the gate of M1 due to M1 and diode connected M3 can be expressed as:
21
23
212
)3,1(
m
nnin
giiv +
=
Where, ( ) fWLCgKgkTi
OX
mNmn
1
21
121
324 +⎟⎠⎞
⎜⎝⎛= and ( ) fWLC
gKgkTiOX
mPmn
3
23
32
3324 +⎟⎠⎞
⎜⎝⎛=
Therefore the total noise referred to the input (gate of M1) is:
( ) ( )2
12
5
23
27
25
21
23
21
21
212
)3,1(2
mm
mnn
m
nn
v
oinin
gggii
gii
Avvv
××+
++
=+= . Therefore for one half-circuit,
( ) ( )2
12
5
23
27
25
23
21
252
mm
mnnnnmin
gggiiiigv
××+++×
=
Considering only the thermal noise, the total input referred noise is:
( ) ( )2
12
5
752
3312
52
)(324
324
2mm
mmmmmm
THERMALingg
ggkTgggkTgv
×
⎥⎦
⎤⎢⎣
⎡+⎟
⎠⎞
⎜⎝⎛+⎥
⎦
⎤⎢⎣
⎡+⎟
⎠⎞
⎜⎝⎛
×=
Considering only the flicker noise, the total input referred noise is:
( ) ( ) ( ) ( )2
12
5
7
27
5
252
33
23
1
212
52
)( 2mm
OX
mN
OX
mPm
OX
mP
OX
mNm
FLICKERingg
fWLCgK
fWLCgKg
fWLCgK
fWLCgKg
v×
⎥⎦
⎤⎢⎣
⎡++⎥
⎦
⎤⎢⎣
⎡+
×=
Equating the thermal noise and flicker noise to find the flicker noise corner frequency (fC), we have:
( ) ( ) ( ) ( )
( ) ( )⎥⎦
⎤⎢⎣
⎡+⎟
⎠⎞
⎜⎝⎛+⎥
⎦
⎤⎢⎣
⎡+⎟
⎠⎞
⎜⎝⎛
=⎪⎭
⎪⎬⎫
⎪⎩
⎪⎨⎧
⎥⎦
⎤⎢⎣
⎡++⎥
⎦
⎤⎢⎣
⎡+
752
3312
5
7
27
5
252
33
23
1
212
5
324
324
1
mmmmmm
COX
mN
OX
mPm
OX
mP
OX
mNm
ggkTgggkTg
fWLCgK
WLCgKg
WLCgK
WLCgKg
Numerical Calculations: All transistors in saturation, (W/L)1,2 = 50/0.6, (W/L)3,4 = 10/0.6, (W/L)5,6 = 20/0.6 and (W/L)7,8 = 56/0.6 µnCOX = 75 µA/V2 and µpCOX = 30 µA/V2 and ISS = 0.5 mA Therefore I1 = I2 = I3 = I4 = 0.25 mA and I5 = I6 = I7 = I8 = 0.5mA
Using DOXm ILWCg ⎟
⎠⎞
⎜⎝⎛= µ2 , we obtain:
gm1 = gm2 = 1.768 mS gm3 = gm4 = 0.5 mS gm5 = gm6 = 1 mS gm7 = gm8 = 2.646 mS Using the above, we obtain, the following values for the thermal and flicker noise powers
HzVv THERMALin
2172)( 10247.2 −×=
Assuming tox= 100A°, we obtain COX = 34.53 x 10-4. Therefore the total flicker noise is given by:
8 22( )
3.2417 10in FLICKER Vv Hzf
−×=
Equating the noise powers to find the flicker noise corner frequency, we obtain: fC = 1.44 GHz.
Problem 3 – (10 points) Assumptions:
• VOD = VGS – VTH • Only thermal noise of drain current considered
Also, we know for a MOS transistor, we have:
OD
D
THGS
Dm V
IVV
Ig 22=
−= and
Do I
rλ
1=
Dynamic range of the circuit is defined as:
outnoise
swingout
VV
DR−
−=
where Vout-swing is the maximum output voltage swing of the amplifier and Vnoise-out is the total output referred voltage noise. We know for a folded cascode amplifier,
1mm gG = and
( )31220544 ooomomout rrrgrrgR = ,
which on expansion, yields
( ) 321231544
5432142
ooomoooom
ooooommout rrrgrrrrg
rrrrrggR++
=
Since from the above, we see that both Gm and Rout are dependent on the over-drive voltage, we need to consider the effect of variation of VOD on both. Substituting for gm and Rout in terms of VOD, we obtain the following expressions for Gm and Rout
OD
Dmm V
IgG 21 ==
DOD IVRout 2
152
λ×=
Expression for output swing in terms of the over-drive voltage: Output swing of a folded cascode amplifier:
ODDDswingout VVV 4−=− Expression for the output referred noise as a function of over-drive voltage: The major noise contributors in the folded cascode amplifier are: M1, M3 and M5. Therefore we first obtain the noise contributions of each of these noise sources at the output.
Vb5
VDD
vout
Vb2M2M1vin
VDD
Vb4M4
M5
M3 Vb3
221
1
2)1(
324 outm
m
outn Rgg
kTv ×⎥⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛=−
223
3
2)3(
324 outm
m
outn Rgg
kTv ×⎥⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛=−
225
5
2)5(
324 outm
m
outn Rgg
kTv ×⎥⎦
⎤⎢⎣
⎡⎟⎟⎠
⎞⎜⎜⎝
⎛=−
Therefore taking the superposition of these noise sources, we have the output referred noise given by:
[ ] 2531
2
324 outmmmoutn RgggkTv ×++×⎟⎠⎞
⎜⎝⎛=−
Therefore substituting expressions for gm and Rout into the above, we obtain the total output referred noise power as:
DOD
outnIV
kTv 43
2 12532
324
λ×⎟⎠⎞
⎜⎝⎛×⎟
⎠⎞
⎜⎝⎛×=−
Therefore the output referred noise voltage can be expressed as a function of VOD as:
( ) 23
1
OD
outnV
Bv ×=−
Dynamic Range calculations: Initial expression for the dynamic range (DR1):
( )( )B
VVVDR ODODDD2
3
14−
=
After the over-drive voltage changes to 75% of its original value, the new dynamic range (DR2) is given by:
( )
B
VVVDR
ODODDD
23
2433 ⎟
⎠⎞
⎜⎝⎛−
=
Therefore, finding the difference between the initial and final dynamic ranges, we can find the variation in the dynamic range caused by 25% reduction in VOD
( )⎥⎦⎤
⎢⎣⎡ −
=−=∆472
3
21ODDDOD VV
BVDRDRDR
Problem 4 – (10 points)
Problem 5 – (10 points)
ECE 6412 - Spring 2006 Page 1
Homework Assignment No. 13 Solutions Problem 1 – (10 points)
Problem 2 – (10 points)
Problem 3 – (10 points)
Problem 4 – (10 points)