Yield Enhancement of 0.25μm GaN HEMT Foundry Technology

Wei-Chou Wang, Jhih-Han Du, Che-Kai Lin, Ming-Hung Weng, Cheng-Wen Peng, Walter Wohlmuth,

WIN Semiconductors Corp, No. 35, Technology 7th Road, Hwaya Technology Park,

Kuei Shan Hsiang, Tao Yuan Shien, Taiwan 333

weichouw@winfoundry.com, Tel +886-3-3975999 ext 1527

Keywords: AlGaN/GaN, field-plate, DRES, ODGATE, T-gate

Abstract

A variety of process developments on the gate module

and design optimization of the EPI structure were

performed to support yield enhancement of 0.25μm GaN

HEMT technology. The technological developments to be

discussed pertain to the results of a gate pre-treatment

DOE experiment, to implement the best condition for

reliability improvement; a gate module process flow

optimization, to minimize DC FET parameter variation;

and the optimization of EPI buffer conditions, to stabilize

the PCM performance and enable larger voltage rating.

The developmental challenges will be elucidated followed

by data showing the trade-off with reliability

performance, stability and control of the critical

parameters for high-yield production purposes.

INTRODUCTION

AlGaN/GaN HEMT have demonstrated excellent RF

device and good reliability performance by many companies

in the world [1~4]. WIN Semiconductors is leveraging the

experience in GaAs pHEMT, HBT and BiHEMT and is

developing AlGaN/GaN HEMTs to broaden WIN

Semiconductors’ foundry services driven by our customer

interests and needs. WIN is a pure play foundry with a

mission to provide our customers Foundry services with the

best yield and cycle time [5]. In 2013, WIN demonstrated

their first 0.25 μ m GaN technology and transistor

performance operating in X-band [6~7] and thereafter a

program to develop high volume production capability in

terms of yield is being executed at WIN Semiconductor. This paper conveys engineering methodologies used to

improve the WAT yield of the 0.25μm GaN process. Since

the 2DEG of GaN HEMT channel is formed by spontaneous

and piezoelectric polarization, it is important to keep a

consistent surface condition during the process. In addition,

the transparent substrate properties and the buffer design are

also need to be taken into consideration. Three methods of

improving the yield in GaN-based devices were proposed in

terms of gate pre-treatment, gate photolithography process

optimization and EPI buffer layer optimization.

PROCESS OPTIMIZATION

The gate pre-treatment process plays an important role in

the front-side process in order to achieve low gate leakage

current and stable device breakdown performance. During

high voltage operation, the interface underneath gate can be

changed due to the high electric field imposed on gate-drain

side which can induce reliability issues. The buffer layer

design and trap density are also important for high drain

voltage operation which could be optimized by using pulsed

IV measurements.

The DOE plan for the gate pre-treatment is shown in

Table 1. Four conditions with different combinations of pre-

treatment approaches were implemented using wet chemical

or plasma-assisted process steps. The gate interface state was

evaluated by pulsed IV measurement as shown in Fig.1. The

DOE4 condition showed a relatively lower drain current

degradation and also a larger capacitance as shown in Fig.2.

The C-V measurement result revealed that different

interfaces are formed for different pre-treatment conditions.

The C-V measurement is also a good index for interface

monitoring during mass production. TABLE I

DOE PLAN OF GATE PRE-TREATMENT

* B1=plasma, B2=plasma, C1=wet chemical

Figure 1: Gate pulse measurement for different pre-treatment conditions

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Figure 2: C-V measurement for different pre-treatment condition (@ 1MHz)

The interface is observed by HAADF STEM imaging as

shown in Fig.3. An extra interface layer was observed for

DOE1 but not in DOE4. The interface material seen in

DOE1 with STEM analysis was primarily Oxygen. Since the

gate interface is quite critical to reliability performance, the

DC-HTOL test is a good method to check the interface

quality. A very significant difference in the DC-HTOL tests

for the DOE conditions was observed as shown in Fig.4. The

transistors were stressed at a peak junction temperature of

250C with 28V drain bias. It is very obvious that the DOE4

condition showed less drain current degradation and this was

correlated to the gate pulse and C-V measurement results.

For further evaluation of the repeatability and performance

of this DOE4 condition, another 20 die were chosen to

continue the test till 500hrs with good results.

Figure 3: HAADF STEM image of the gate interface for DOE1 and DOE4.

An oxide material layer is detected in DOE1.

(a)

(b)

Figure 4: DC-HTOL test of (a) different DOE conditions, and (b) DOE4

condition with 20 die to confirm reliability performance till 500hrs. The test

conditions included 28V drain bias and Tj=250C

After running prototype production volume with the

DOE4 pre-treatment condition, the variation of gate leakage

and breakdown voltage was identified as the major yield

killers. The root cause for the yield issue was a narrow

process window of photo-resist coverage after gate metal

formation as shown in Fig.5(a).

(a)

66 CS MANTECH Conference, May 19th - 22nd, 2014, Denver, Colorado, USA

(b)

Figure 5: (a) SEM image of normal and abnormal photo-resist coverage, (b)

Process flow comparison before and after optimization

The abnormal PR coverage profile was caused by un-

certain and varying ohmic edge profile. The use of negative

photo-resist with GaN/SiC significantly alters

photolithography dose, cure and focus offset conditions as

negative photo-resist relies on optical backscatter from the

substrate and EPI to form the PR profile. Since the optical

backscatter is very small for a low refractive index and

transparent material system, the photolithography

parameters need to be fine tuned and modified for GaN.

Thus the 2nd

SiN first deposition process was implemented

with the intent to enlarge the process window as shown in

Fig. 5 (b). The WAT trend chart showed a very promising

result after this process change was implemented as shown

in Fig.6. A stable breakdown (VDG) and gate leakage (IPO)

performance was obtained after process optimization. This

process change also enabled an improvement in threshold

voltage shift and Gm swing with changing drain bias from

10V to 50V as shown in Fig.7. 10GHz pulsed load-pull at

Vd=28V was measured for a 1.25mm transistor. The result

showed that the process technology could realize transistors

with P.A.E. above 50% and with output power density of

4.8W/mm.

(a)

(b)

Figure 6: PCM trend chart comparison of (a) breakdown voltage, and (b) gate leakage current biased @ Vd=10V and Vg=-5V

(a)

(b)

Figure 7: Transfer curve comparison of (a) original process flow and (b)

after process change

Figure 8: Pulse load-pull performance @ 10GHz with pulse width=12.5μ

sec, duty cycle=1%. 28V drain bias and Idq=20mA

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Finally, an EPI buffer DOE design with different buffer

doping profiles to get high ruggedness performance and

voltage rating was done. The DOE plan including doping

concentration, doping ramp rate and distance from doping to

2DEG are shown in Table II. The improvement in gate

leakage and breakdown stability was shown in Fig.9. It is

obvious that buffer condition 2 showed a more stable

breakdown performance in terms of the measurement

compliance voltage of 160V. This new buffer design enables

transistor operating bias to be up to 50V and has

applicability in future base-station applications and products.

TABLE II

DOE PLAN OF EPI BUFFER DESIGN

(a)

(b)

(c)

(d)

Fig.9 RF PCM performance of (a) gate leakage (IPO), (b) breakdown voltage (VDG), (c) cut-off frequency (ft), and (d) maximum stable gain

(MSG) @ Vd=28V with different EPI buffer layer design

CONCLUSIONS

In this paper, the improvement of WAT yield in terms of

gate process and EPI design was conveyed. The objective is

to enhance the high volume production capability for GaN

technology.

ACKNOWLEDGEMENTS

The authors would like to thank all the members who

supported the GaN technology development in WIN

including the characterization, manufacturing, and quality

control teams, respectively.

REFERENCES

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[2] R. J. Trew, D. S. Green, and J. B. Shealy, “AlGaN/GaN HFET

reliability”, IEEE Microwave Magazine, pp. 116-127, June, 2009.

[3] R. S. Pengelly, S. M. Wood, J. W. Milligan, S. T. Sheppard, W. L.

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[7] W. C. Wang, C. H. Chen, J. H. Du, M. H. Weng, C. K. Lin, C. C. Huang, C. C. Chang, S. H. Huang, Y. F. Wei, Y. C. Hsieh, M. Casbon, P. J.

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ACRONYMS

HEMT: High Electron Mobility Transistor

SFP: Source-coupled Field-Plate

MSG: Maximum Stable Gain

WAT: Wafer Acceptance Test

PCM: Process Control Monitor

CD: Critical Dimension

HTOL: High Temperature Operation Lifetime

HAADF: High Angle Annular Dark Field

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