Tittle: Application of High-κ Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology

Authors: Robert Chau, Justin Brask, Suman Datta, Gilbert Dewey, Mark Doczy,Brian Doyle, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar, and Marko Radosavljevic

Nasir KhanELEN279-Summer’12

Affiliation: Components Research Technology and Manufacturing Group, Intel CorporationMail Stop RA3-252, 5200 NE Elam Young Parkway, Hillsboro, OR 97124 Email: robert.s.chau@intel.com

14th Biennial Conference on Insulating Films on Semiconductors Leuven, Belgium. 22-24 June 2008 (press release)

Abstract

High-κ gate di-electrics and metal gate electrodes are required for:Continued equivalent gate-oxide thickness scaling

(Transistor scaling with increased performance and reduced power consumption).

Controlling gate-oxide leakage for both future Si and evolving non-Si Nano-electronic transistors.

High-κ gate dielectrics and metal gates are also required for the successful demonstration of:High performance logic transistors on high mobility

non-Si substrates with high ION/IOFF ratios.

Introduction Silicon Industry is scaling SiO2 for the past few decades and still

continuing.

Continued gate-oxide scaling is becoming difficult because:Gate-oxide leakage is increasing with decreasing SiO2

thicknessSiO2 is running out of atoms for further scaling

As Moore’s law extends scaling and device performance, High-κ gate dielectrics and metal gate electrodes will be required (45nm & beyond CMOS application) for:High performanceLow power consumption

In addition, the high-k and metal gate combination is important to enable high performance and low gate-leakage emerging transistors built on non-Si high mobility materials including:GermaniumCarbon nanotubesGroup III-V substrate

High-k/metal gate combinationHigh-κ/Poly-Si gate not suitable for high performance logic

applications Resulting transistors have high threshold voltages degrading voltage

High-κ/metal gate for Si Nano-transistors Phonon scattering is greater using a high-k/poly-Si dielectric This leads to decreased channel mobility Use of a metal gate can help increase the surface mobility

High-k/metal gate combinationThreshold Voltage Pinning- high-k and Poly-Si gate are

incompatible due to Fermi level pinning at the High-k and Poly-Si interface which causes high threshold voltages in transistors.

Phonon scattering - High-κ/ Poly-Si transistors exhibit severely degraded channel mobility due to the coupling of phonon modes in high-K to the inversion channel charge carriers.

High-k/metal gate combination High-κ phonons and gate plasmons modeled as electric dipoles

Doped poly-Si gate (~1018/cm3) when Etot < Egate-plasmon < Elo: in-resonance occurs which degrades channel mobility.

Metal gate (>1020/cm3) : Off-resonance condition weakens carrier coupling, hence the channel mobility is recovered.

High-k/metal gate combination Metal gate electrodes are able to decrease phonon

scatterings and reduce the mobility degradation problem. Requires metal gate electrodes with correct work functions

on High-κ for both n-MOS and p-MOS transistors for high performance.

High-k/metal gate combinationHigh-κ/metal gate CMOS transistors on bulk silicon with 1.0 nm

equivalent oxide thickness have been demonstrated using an n+ work function metal electrode for the NMOS transistor and a p+ work function metal electrode for the PMOS transistor.

The resulting High-κ/metal gate transistors exhibit good channel electron and hole mobility, correct n-channel and p-channel threshold voltages, and the expected high drive current performance for both the NMOS and PMOS transistors.

Breakthroughs with Metal Gates

N-Type metal and P-Type metal with the CORRECT work functions on High-κ have been engineered.

High-κ\metal-gate stack achieves n-MOS and p-MOS channel mobility close to SiO2's.

High-κ\metal-gate stack shows significantly lower gate leakage than SiO2.

High-κ/Metal-Gate for Emerging Nano-electronic Devices

High-κ/metal gate combination is also important for enabling future high-performance and low gate-leakage emerging Nano-electronic transistors.

High-κ dielectrics have been demonstrated to be more compatible with some of these non-silicon substrates(e.g., Germanium) versus their compatibility with conventional SiO2. High-performance carbon nanotube field-effect transistors

(CNTFETs) with very low gate dielectric leakage can also be fabricated with the use of high-κ/metal gate.

High-κ/Metal-Gate for Emerging Nano-electronic Devices High-κ dielectrics for emerging III-V transistors, such

as InSb quantum-well transistors is illustrated. Compared to standard Si devices, the InSb transistor shows much

improved n-channel intrinsic speed (CV/I) due to higher channel mobility.

Conclusion

High-κ gate dielectrics and metal gate electrodes are required for:Enabling continued equivalent gate oxide thickness scaling

High performance Controlling gate oxide leakage

High-κ gate dielectrics and metal gates are required for successful demonstration of high performance logic transistors on high-mobility non-silicon substrates with high ION /IOFF ratios.

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