TDA2005

20W BRIDGE AMPLIFIER FOR CAR RADIO

September 2003

1

2

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7

9

10

11

8

BOOTSTRAP(1)

INPUT-(1)

SVRR

GND

INPUT-(2)

INPUT+(2)

OUTPUT(2)

+VS

OUTPUT(1)

INPUT+(1)

TAB CONNECTED TO PIN 6 D95AU318

BOOTSTRAP(2)

PIN CONNECTION

MULTIWATT11

ORDERING NUMBERS : TDA2005M (Bridge Appl.) TDA2005S (Stereo Appl.)

High output power : PO = 10 + 10 W@RL = 2, d =10% ; PO = 20W@RL = 4 , d = 1 %.High reliability of the chip and package with addi-tional complete safety during operation thanks toprotection against : .OUTPUT DC AND AC SHORT CIRCUIT TO

GROUND.OVERRATING CHIP TEMPERATURE .LOAD DUMP VOLTAGE SURGE .FORTUITOUS OPEN GROUND .VERY INDUCTIVE LOADSFlexibility in use : bridge or stereo booster amplifi-ers with or without boostrap and with programma-ble gain and bandwidth.Space and cost saving : very low number of exter-nal components, very simple mounting system withno electrical isolation between the package and theheatsink (one screw only).In addition, the circuit offers loudspeaker protec-tion during short circuit for one wire to ground.

DESCRIPTION

The TDA2005 is class B dual audio power amplifierin MULTIWATT package specifically designed forcar radio application : power booster amplifiersare easily designed using this device that providesa high current capability (up to 3.5 A) and that candrive very low impedance loads (down to 1.6 in

ABSOLUTE MAXIMUM RATINGSSymbol Parameter Value Unit

Vs Operating Supply Voltage 18 VVs DC Supply Voltage 28 VVs Peak Supply Voltage (for 50 ms) 40 V

Io (*) Output Peak Current (non repetitive t = 0.1 ms) 4.5 AIo (*) Output Peak Current (repetitive f 10 Hz) 3.5 APtot Power Dissipation at Tcase = 60 C 30 W

Tstg, Tj Storage and Junction Temperature 40 to 150 C(*) The max. output current is internally limited.

1/18

SCHEMATIC DIAGRAM

THERMAL DATA

Symbol Parameter Value Unit

Rth j-case Thermal Resistance Junction-case Max. 3 C/W

TDA2005

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Figure 1 : Test and Application Circuit (Bridge amplifier)

Figure 2 : P.C. Board and Components Layout of Figure 1 (1:1 scale)

BRIDGE AMPLIFIER APPLICATION (TDA2005M)

TDA2005

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ELECTRICAL CHARACTERISTICS (refer to the Bridge application circuit, Tamb = 25oC, GV = 50dB,Rth (heatsink) = 4oC/W, unless otherwise specified)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vs Supply Voltage 8 18 V

Vos Output Offset Voltage (1)(between pin 8 and pin 10)

Vs = 14.4VVs = 13.2V

150150

mVmV

Id Total Quiescent Drain Current Vs = 14.4V RL = 4Vs = 13.2V RL = 3.2

7570

150160

mAmA

Po Output Power d = 10% f = 1 HzVs = 14.4V RL = 4

RL = 3.2Vs = 13.2V RL = 3.2

182017

202219

W

d Distortion f = 1kHzVs = 14.4V RL = 4Po = 50mW to 15WVs = 13.2V RL = 3.2Po = 50mW to 13W

1

1

%

%

Vi Input Sensitivity f = 1kHzPo = 2W RL = 4 Po = 2W RL = 3.2

98

mVmV

Ri Input Resistance f = 1kHz 70 kfL Low Frequency Roll Off ( 3dB) RL = 3.2 40 Hz

fH High Frequency Roll Off ( 3dB) RL = 3.2 20 kHzGv Closed Loop Voltage Gain f = 1kHz 50 dB

eN Total Input Noise Voltage Rg = 10k (2) 3 10 VSVR Supply Voltage Rejection Rg = 10k, C4 = 10F

fripple = 100Hz, Vripple = 0.5V45 55 dB

h Efficiency Vs = 14.4V, f = 1 kHzPo = 20W RL = 4Po = 22W RL = 3.2Vs = 13.2V, f = 1 kHzPo = 19W RL = 3.2

6060

58

%%

%

Tj Thermal Shut-down JunctionTemperature

Vs = 14.4V, RL = 4f = 1kHz, Ptot = 13W

145 C

VOSH Output Voltage with one Side ofthe Speaker shorted to ground

Vs = 14.4V RL = 4Vs = 13.2V RL = 3.2 2 V

Notes : 1. For TDA2005M only2. Bandwith Filter : 22Hz to 22kHz.

TDA2005

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Figure 5 : Distortion versus Output Power(bridge amplifier)

BRIDGE AMPLIFIER DESIGNThe following consideraions can be useful when designing a bridge amplifier.

Parameter Single Ended Bridge

Vo max Peak Output Voltage (before clipping)12

(Vs 2 VCE sat) Vs 2 VCE sat

Io max Peak Output Current (before clippling)12

VS 2 VCE sat

RL

VS 2 VCE satRL

Po max RMS Output Power (before clipping)14

(VS 2 VCE sat)2

2 RL

(VS 2 VCE sat)2

2 RL

Where : VCE sat = output transistors saturation voltageVS = allowable supply voltageRL = load impedance

Figure 3 : Output Offset Voltage versusSupply Voltage

Figure 4 : Distortion versus Output Power(bridge amplifier)

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Voltage and current swings are twice for a bridgeamplifier in comparison with single ended amplifier.In order words, with the same RL the bridge con-figuration can deliver an output power that is fourtimes the output power of a single ended amplifier,while, with the same max output current the bridgeconfiguration can deliver an output power that istwice the output power of a single ended amplifier.Core must be taken when selecting VS and RL inorder to avoid an output peak current above theabsolute maximum rating.From the expression for IO max, assuming VS= 14.4V and VCE sat = 2V, the minimum load thatcan be driven by TDA2005 in bridge configurationis :

RL min = VS 2 VCEsat

IO max =

14.4 43.5

= 2.97

The voltage gain of the bridge configuration is givenby (see Figure 34) :

GV = V0V1

= 1 + R1

R2 R4R2 + R4

+ R3R4

For sufficiently high gains (40 to 50dB) it is possibleto put R2 = R4 and R3 = 2 R1, simplifing the formulain :

GV = 4 R1R2

Gv (dB) R1 () R2 = R4 () R3 ()4050

10001000

3912

20002000

Figure 6 : Bridge Configuration

Figure 7 : Typical Application Circuit

STEREO AMPLIFIER APPLICATION (TDA2005S)

TDA2005

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ELECTRICAL CHARACTERISTICS (refer to the Stereo application circuit, Tamb = 25oC, GV = 50dB,Rth (heatsink) = 4oC/W, unless otherwwise specified)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Vs Supply Voltage 8 18 V

Vo Quiescent Output Voltage Vs = 14.4VVs = 13.2V

6.66

7.26.6

7.87.2

VV

Id Total Quiescent Drain Current Vs = 14.4VVs = 13.2V

6562

120120

mAmA

Po Output Power (each channel) f = 1kHz, d = 10%Vs = 14.4V RL = 4

RL = 3.2RL = 2RL = 1.6

Vs = 13.2V RL = 3.2RL = 1.6

Vs = 16V RL = 2

6791069

6.5810116.51012

W

d Distortion (each channel) f = 1kHzVs = 14.4V RL = 4Po = 50mW to 4WVs = 14.4V RL = 2Po = 50mW to 6WVs = 13.2V RL = 3.2Po = 50mW to 3WVs = 13.2V RL = 1.6Po = 40mW to 6W

0.2

0.3

0.2

0.3

1

1

1

1

%

%

%

%

CT Cross Talk (1) Vs = 14.4V, Vo = 4VRMSRL = 4, Rg = 5k

f = 1kHzf = 10kHz

6045

dB

Vi Input Saturation Voltage 300 mV

Vi Input Sensitivity f = 1kHz, Po = 1WRL = 4RL = 3.2

65.5

mV

Ri Input Resistance f = 1kHz 70 200 kfL Low Frequency Roll Off ( 3dB) RL = 2 50 HzfH High Frequency Roll Off ( 3dB) RL = 2 15 kHz

Gv Voltage Gain (open loop) f = 1kHz 90 dB

Gv Voltage Gain (closed loop) f = 1kHz 48 50 51 dB

D Gv Closed Loop Gain Matching 0.5 dB

eN Total Input Noise Voltage Rg = 10k (2) 1.5 5 VSVR Supply Voltage Rejection Rg = 10k, C3 = 10F

fripple = 100Hz, Vripple = 0.5V35 45 dB

h Efficiency Vs = 14.4V, f = 1kHzPo = 6.5W RL = 4Po = 10W RL = 2Vs = 13.2V, f = 1kHzPo = 6.5W RL = 3.2Po = 100W RL = 1.6

7060

7060

%%

%%

Notes : 1. For TDA2005M only2. Bandwith Filter : 22Hz to 22kHz.

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Figure 10 : Distortion versus Output Power(Stereo amplifier)

Figure 8 : Quiescent Output Voltage versusSupply Voltage (Stereo amplifier)

Figure 9 : Quiescent Drain Current versusSupply Voltage (Stereo amplifier)

Figure 11 : Output Power versus Supply Voltage(Stereo amplifier)

Figure 12 : Output Power versus Supply Voltage(Stereo amplifier)

Figure 13 : Distortion versus Frequency(Stereo amplifier)

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Figure 14 : Distortion versus Frequency(Stereo amplifier)

Figure 15 : Supply Voltage Rejection versus C3(Stereo amplifier)

Figure 16 : Supply Voltage Rejection versusFrequency (Stereo amplifier)

Figure 17 : Supply Voltage Rejection versusC2 and C3 (Stereo amplifier)

Figure 18 : Supply Voltage Rejection versusC2 and C3 (Stereo amplifier)

Figure 19 : Gain versus Input Sensitivity(Stereo amplifier)

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Figure 20 : Gain versus Input Sensitivity(Stereo amplifier)

Figure 21 : Total Power Dissipation and Efficiencyversus Output Power(Bridge amplifier)

Figure 22 : Total Power Dissipation and Efficiencyversus Output Power(Stereo amplifier)

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Comp. Recom.Value Purpose Larger Than Smaller Than

R1 120 k Optimization of the OutputSymmetry

Smaller Po max Smaller Po max

R2 1k

R3 2 k

R4, R5 12 Closed Loop Gain Setting (seeBridge Amplifier Design) (*)

R6, R7 1 Frequency Stability Danger of Oscillation at HighFrequency with Inductive Loads

C1 2.2 F Input DC Decoupling

C2 2.2 F Optimization of Turn on Pop andTurn on Delay

High Turn on Delay Higher Turn on Pop, HigherLow Frequency Cut-off,Increase of Noise

C3 0.1 F Supply by Pass Danger of Oscillation

C4 10 F Ripple Rejection Increase of SVR, Increase ofthe Switch-on Time

Degradation of SVR.

C5, C7 100 F Bootstrapping Increase of Distortionat low Frequency

C6, C8 220 F Feedback Input DC Decoupling,Low Frequency Cut-of