194 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

Demonstration of 10-μm Microvias in ThinDry-Film Polymer Dielectrics for

High-Density InterposersYuya Suzuki, Ryuta Furuya, Venky Sundaram, and Rao R. Tummala, Fellow, IEEE

Abstract— This paper describes the demonstration of 10-µmdiameter interlayer vias with 3.5-µm wide re-distribution layercopper wiring in a unique dry-film polymer dielectric, ZEONIFZS100 (ZS100), suitable for panel-based high-density organic andglass interposers. The uniqueness of polymer dielectric includeslow dielectric constant, low dielectric loss, low moisture uptake,and low surface roughness. The dry-film polymer dielectric waslaminated on thin and low coefficient of thermal expansionorganic or glass cores using double-side vacuum laminationprocesses. The ultrasmall microvias were drilled with 248-nmKrF excimer laser. Metallization by electroless and electrolyticcopper plating successfully achieved formation of fully filledvias and copper traces simultaneously without any chemical–mechanical polishing. The processes demonstrated in this paperenable interposers with much finer bump pitch than currentorganic package technology. In addition, the processes can bescaled to large panels leading to lower cost than the previouswork in fine pitch Si interposers fabricated through back-end-of-line wafer processes.

Index Terms— Excimer laser, fine pitch via, fine pitch wiring,microvia, thin dielectric film.

I. INTRODUCTION

GROWING demand for high-speed electronic systemshas driven the need for ultrahigh density wiring to

interconnect two or more ICs either in vertical direction suchas by 3-D stack of ICs with through silicon via or in hor-izontal direction by 2.5-D interposers. Such ultrahigh multi-layer wiring for 2.5-D interposers requires ultrasmall diameterinterlayer microvias. Silicon interposers have been developedand commercialized to meet such demands using back-end-of-line processes using silicon dioxide or nitride dielectric layerswith submicrometer lithographic lines and vias by damasceneor dual-damascene processes [1], [2]. Silicon interposers have

Manuscript received September 5, 2014; revised November 17, 2014;accepted December 12, 2014. Date of publication January 21, 2015; dateof current version February 3, 2015. This work was supported by theU.S. Department of Commerce under Grant BS123456. Recommended forpublication by Associate Editor J. J. Liu upon evaluation of reviewers’comments.

Y. Suzuki is with the 3D Packaging Research Center, Georgia Instituteof Technology, Atlanta, GA 30332 USA, and also with the Research andDevelop Center, Zeon Corporation, Kawasaki 210-9507, Japan (e-mail:ysuzuki3@mail.gatech.edu).

R. Furuya is with Ushio Inc., Tokyo 100-8150, Japan (e-mail:rfuruya3@mail.gatech.edu).

V. Sundaram and R. R. Tummala are with the 3D Packaging ResearchCenter, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail:vs24@mail.gatech.edu; rao.tummala@ece.gatech.edu).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2014.2382339

also been fabricated with photosensitive dielectric materials forwafer level packaging applications to achieve below 10-μmvias [3], [4]. Shinko, for example, has applied liquid pho-tosensitive processes to demonstrate 2-μm lines and 10-μmdiameter vias [5]. Since these processes are single sided anddesigned for small 300-mm wafers, these interposers tendto be expensive. In contrast, organic packaging technologyprovides a lower cost approach with large panel sizes of500 mm, utilizing thin dry-film build-up polymer dielectricmaterials, yielding 8× more packages than from 300-mmwafers [6]. However, fabrication of small microvias at finepitch and registration of these vias from layer to layer are twobarriers to high-density interconnections in organic and otherpackages. Current organic package manufacturing technol-ogy is at 15-μm wiring with 40–50-μm microvias, usingCO2 laser drilling and semi-additive process (SAP). Limitingfactors in reducing via diameters include long wavelength(10.2 and 10.6 μm) and large CO2 laser beam focus(60–70 μm). Recent advances in packaging processes suchas SAP and Nd-YAG lasers led to the demonstration of 9-μmlithography and 25-μm microvias [7]. Kyocera has demon-strated high density organic interposers with 8 μm linelithography and 25 μm dia. micro-vias drilled with266 nm Nd-YAG laser [8]. Kyocera recently achievedeven smaller, 20 μm micro-vias, by optimization ofthe Nd-YAG laser parameters. To achieve even smallerdimensions, new advances have been proposed and reported.Atotech and Amkor, for example, have developed Via2

processes to demonstrate 10-μm line features with trenchfilling processes using excimer laser and copper platingprocesses [16], [17]. Fujikura reported one of the mostadvanced trench circuit technologies to demonstrate 2-μmlinewidth and 10-μm microvia diameter [18]. However,trench filling processes require an expensive chemical–mechanical polishing, thus limiting their applicability to largepanels.

This paper reports advances to form 10-μm diametermicrovias in 10-μm thick polymer build-up dry films toapply to large panel manufacturing. Table I shows a summaryof microvia hole formation processes in thin film dielectricmaterials. Laser drilling processes have been widely used toform microvia openings because laser processes can makemicrovias in various dielectric materials, enabling wider mate-rial selection. Conventional serial-laser drilling, such as CO2and Nd-YAG laser processes have difficulty in making small

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SUZUKI et al.: DEMONSTRATION OF 10-μm MICROVIAS IN THIN DRY-FILM POLYMER DIELECTRICS 195

TABLE I

VIA FORMATION IN FILM MATERIAL BY VARIOUS METHODS

size vias especially below 15 μm, because of the thermaldamage they cause. In addition, these serial processes cancreate only single via at a time, which limits the throughput.In contrast, excimer laser is compatible with mask projectionprocesses, which enables formation of multiple vias simulta-neously. This ability to form multiple vias at the same timeis beneficial for high throughput and for registration betweenvias. Furthermore, excimer lasers have a potential to providethe smallest vias because of minimum thermal damage. In thispaper, the reported research in [13] has been extended and inaddition, a detailed analysis of the influence of via openingsize in filled plating processes is implemented. As a result,successful demonstration of ultrasmall microvias and copperwirings layers has been achieved. Section I describes the thinpolymer dry-film material and lamination processes. Section IIdiscusses the ultrasmall via formation by KrF excimer laserprocesses. Section III illustrates the method for via metalliza-tion by electroless and electrolytic plating processes. Finally,demonstration of fine pitch microvia and wiring is describedin Section IV as the conclusion. The processes developed inthis paper are aimed at panel-based processing to form thebasis of 50-μm bump pitch re-distribution layer (RDL) wiringin organic and glass interposers.

II. DIELECTRIC MATERIAL AND PROCESS

A. Polymer Dielectric Material

Polymer dielectrics must meet a variety of electrical,thermal, mechanical, and chemical properties. In addition,it must be easily processable with an excellent adhesion tocopper and other substrate materials. The ZEONIFZS100 (ZS100) polymer dry film [19] was selected based onmeeting these requirements, as the RDL build-up materialin this paper. It is a low loss material and is compatiblewith SAPs to form copper seed layers with smooth interface.In addition, multilayer RDL structure formation is capableof using ZS-100 because it has high flow during laminationprocess and microvia can be drilled with a variety of laserprocesses [20], [21]. Properties of the fully cured ZS100

TABLE II

PROPERTIES OF POLYMER (ZS100) USED IN THIS PAPER

Fig. 1. Difference in surface roughness in ZS100 and existing material.

polymer dielectric material are summarized in Table II. It hasboth a low dielectric constant (Dk) and a low electricalloss (Df), which are beneficial for high-speed transmission.In addition, its low moisture absorption contributes to highreliability of the package, especially when the package getsthinner. Other outstanding advantage is its strong chemicalbond to electroless plated copper seed layers with a very lowsurface roughness (Ra < 100 nm) (Fig. 1). This extremelysmooth surface is beneficial to form fine line wiring resultingin less copper conductor undercut in forming 3-μm linerouting structures, as shown in Fig. 2 [22].

196 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

Fig. 2. Fine pitch 3-μm routing structures on ZS100.

B. Dielectric Film Formation

The 10-μm thick polymer dry films were laminated onboth sides of the copper clad FR-4 core laminate by vacuumlamination at 100 °C. The copper surfaces of copper cladlaminate were roughened by standard chemical treatmentsbefore the lamination process to enhance adhesion. Thesepanels were hot pressed for 90 s at 3 MPa to planarize thesurface of the dielectric. After lamination, the samples werethermally cured in an oven, ramping up from room temperatureto 180 °C, and held at 180 °C for 30 min. The ZS100 dry filmswere also laminated on other cores such as 100-μm thicknesslow coefficient of thermal expansion glass cores, using vacuumlamination and subsequent hot press processes. The glass corehas a 5-μm thick layer of electrolytic plated copper on bothsides. No significant damage to the glass or organic panelswas observed.

III. MICROVIA FORMATION

A. Ultrasmall Via Drilling by Excimer Laser

Creating ultrasmall microvias below 10-μm size, asdescribed above, is extremely challenging for the serial laserssuch as CO2 and Nd-YAG UV lasers. Limitation of CO2laser comes from the long wavelength (10.2 and 10.6 μm)and large laser beam focus (60–70 μm). These challengeshave been addressed by Nd-YAG UV lasers. However,Nd-YAG lasers induce thermal damage because of their largepower distribution within the laser beam. Furthermore, theseserial laser processes can only achieve positional accuracyof ±8 μm, which hinders their application to fine pitchinterposers. Photolithographic formation of vias in liquidphotosensitive dielectrics has also been explored to achievesub-10-μm vias. However, these dielectrics require sputter-deposited barriers and seed layers. In addition, the processesfor liquid materials are single sided, thus limiting the scal-ability to large panels, thereby resulting in an increasedprocess cost. In this paper, excimer laser ablation processwas developed to form ultrasmall vias for the followingreasons: 1) high absorption by polymer to generate chem-ical interactions for efficient drilling; 2) minimal ther-mal damage to the dielectric material, enabling clean andsmall vias; 3) the availability of projection tools for highthroughput and large panel scaling; and 4) mask projectionprocesses enabling higher positional accuracy between thevias [23], [24]. It is important to match the wavelengthof the laser source to the peak absorption of the polymerto minimize the thermal effects and damage. The selectedZS100 polymer has a characteristic absorption at 250-nm

Fig. 3. Schematic of KrF excimer laser system Optec/Coherent LPX210i.

wavelength. Light absorbance at 250 nm is 4× of the lightabsorbance at 355 nm (2.0 at 250 nm and 0.5 at 355 nm).This means the absorption efficiency of KrF excimer laser isseveral orders of magnitude higher than Nd-YAG laser thirdharmonics. Excimer laser with shorter wavelength such asArF (193 nm) or F2 (157 nm) can drill microvias as well. How-ever, there are some concerns with these shorter wavelengthlaser systems. First, strong light absorption of copper conduc-tors results in damage to the bottom copper pad during thelaser process. Second, due to the absorbance of oxygen in theair during the laser drilling processes, these systems need tobe equipped with inert atmosphere, such as nitrogen or argonin the optical path. For these reasons, KrF excimer laser with248-nm wavelength was selected as a highly efficient laser forvia drilling in the polymer dielectric. When these laser beamsirradiate polymer samples, attenuation of light intensity (I )takes place, as described by (1), where α is the absorbanceof the material at the wavelength, z is the penetration depth,and I0 is the initial light intensity

I (z) = I0exp(−αz). (1)

Absorbed energy per unit mass Em is calculated by (tp is thelaser pulsewidth and ρ is the density of mass)

Em(z) = I (z)tpα/ρ (2)

where Em should be larger than the threshold energy Eth toobtain ablation of the material. Threshold light intensity Ith iscalculated by Ith = ρEth/αtp .

Ablation ratio per one pulse La ∼ z can be assessed by

La = 1

αln

(I

Ith

). (3)

To ensure via formation by laser drilling, laser systems withhigher power than threshold energy of the material is required.On the other hand, too much fluence has a negative effect,such as a larger via opening than designed and distortion ofthe via shape. In this paper, a 248-nm KrF excimer lasersystem (Coherent LPX210i, Fig. 3) with 1 mm × 1-mmbeam size at 200-mJ fluence was used for microvia drilling.A 1′′ × 1′′ quartz mask with sputtered aluminum opening of a10 × 10 array (opening size of 100 μm at 500-μm pitch) was

SUZUKI et al.: DEMONSTRATION OF 10-μm MICROVIAS IN THIN DRY-FILM POLYMER DIELECTRICS 197

Fig. 4. Depth of via versus number of laser shots.

Fig. 5. Vias drilled by excimer laser. (a) SEM of focus view.(b) Cross-sectional view.

projected onto the samples. The mask image was demagnifiedby a factor of 10×, therefore 100-μm opening in the masknarrowed down to 10-μm beam spot size on the samples.Operation frequency of the laser was 100 Hz.

To check the speed of excimer laser drilling processes,varying time of laser shots were applied to the samples.In each case, depth of the vias was measured with confocalmicroscope (Fig. 4). After 10 shots, bottom copper pad wasnot revealed and the depth of the ablated part in polymer layerwas only 5–6 μm (ablation rate of the laser process per shotcan be calculated as 0.5–0.6 μm/pulse). Irradiation of 20 ormore shots were needed to expose copper pads at the bottomto form microvias. These samples were optically inspectedand vias with 20 or more laser shots were fully open. In thefollowing experiments, all the vias were drilled with 20 shotsof laser ablation. From the SEM image in Fig. 5(a), the copper

Fig. 6. Microvia stacked and staggered structures.

Fig. 7. Minimum surface copper thickness to achieve fully filled via forvarious via sizes.

at the bottom of via hole is exposed as the multigrainedcopper structure is shown. The shape of the vias is cleanas expected due to the nonthermal processing of excimerlasers. Cross section of the formed-laser via is shown inFig. 5(b). (Thin copper seed layer was deposited on the build-up layer to make the interface more visible.) No significantdamage to the bottom copper pad was observed after the laserprocess.

B. Via Metallization

Metallization of the microvia was carried out by electrolesscopper plating followed by electrolytic copper plating. Afterdesmear of the drilled samples, Pd-catalyzed electroless copperplating process was applied to form 0.5-μm thick copperseed layers. For ultrafine pitch interposer applications, fillingthe microvia completely by copper is a critical requirementsince fully filled vias can form stacked-via structures, whileconformally plated vias are only compatible with staggered-viastructures as shown in Fig. 6, which require larger space thanstacked structures. Copper via filling behavior can be depen-dent on the size of via openings during electrolytic plating.To confirm this effect, samples with different via openings(10, 15, 20, 30, and 40 μm) were prepared and examined.DC electrolytic plating with InPro A300 (Atotech) was per-formed at the constant current density of 1.0 A/dm2 withchanging plating time. Fig. 7 shows the minimum thicknessof copper to achieve fully filled vias. This graph indicatessmaller sized vias can be filled faster, resulting in thinnercopper on top of the samples after the plating process. Vias of

198 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

Fig. 8. Top-view and cross-sectional view of the fully filled plated vias.

Fig. 9. SAP sequences of the samples with fine pitch vias and wirings.

10-μm diameter have been filled after 30 min of plating, whichresulted in 7-μm thick copper on top of the sample surfaces.Vias of 15-μm diameter were completely filled after 40 minof plating, with 10-μm thick copper on the surface of thesamples. After 1 h of plating, vias of 20 and 30-μm diameterwere filled successfully with 15-μm thick copper on top. To fillcopper into 40-μm diameter microvias completely, more than20 μm of copper ends up being plated on the surface. Fromthese results, if the desired thickness of the surface copper isbelow 8 μm, via diameter needs to be 10 μm.

After 60 min of dc electrolytic plating, fully filled viaswere successfully fabricated (Fig. 8). Thickness of the copperdeposited on top was 8 μm, which is thinner than the generalthickness of the dry-film photoresist (15–20 μm) used for the

Fig. 10. (a) Top view and (b) cross section of the filled via (10 μm indiameter) and fine pitch wiring (3.5-μm width line and 4.5-μm space).Dashed white line in (a) indicates the location of the microvia and dashed redline indicates where cross-sectioned and picture (b) were taken.

SAP process. Furthermore, there are no dimples on top ofthe vias and high surface planarity was achieved. Therefore,this technology can be suitable to form a combination of fine-pitch microvias and solid copper layers to form wiring in onestep by SAP, without polishing processes. Copper filling byelectrolytic plating process was successfully performed due tothe small size of the drilled vias in the thin dielectric material.

C. Fine Pitch Via and Wiring

By integrating the processes described in the previoussections, simultaneous fabrication of filled vias and surfacecopper that can be photoprocessed to form RDL wiringsubsequently, was explored as described in the following(schematic of the process shown in Fig. 9).

1) Lamination of 10-μm thick ZS100 on glass or organiccore.

2) Drilling of microvias (10-μm diameter) by KrF excimerlaser.

3) Plating electroless copper seed layer.4) Applying photo lithography for patterning (15-μm thick

dry-film negative photoresist).

SUZUKI et al.: DEMONSTRATION OF 10-μm MICROVIAS IN THIN DRY-FILM POLYMER DIELECTRICS 199

5) Plating electrolytic copper (1.0-A/dm2, 40 min) to fillmicrovias and to form lithographic patterns.

6) Stripping photoresist.7) Removing copper seed layer by microetching.In this trial, 3′′ × 3′′ size panel was used for an initial trial.

After these processes, an SEM picture was taken, as shownin Fig. 9. Vias with 10-μm diameter were completely filled byplated copper and 3.5-μm line 4.5-μm space with 7-μm highcopper conductors were successfully fabricated. Fig. 10 showsthe cross section of the fabricated samples.

IV. CONCLUSION

In summary, ultrasmall 10-μm microvias were successfullyformed in 10-μm thick dry-film dielectrics by mask projectionexcimer laser processes. These small vias can be completelyfilled with copper plating processes with 8-μm thick copper ontop to form subsequent wiring structures. Due to thin copperon the top surface, simultaneous filling of 10-μm vias andformation of 3.5-μm wide wiring were successfully achievedusing SAP without any surface planarization after plating.It should be noted that the processes demonstrated in thispaper are scalable to larger panels (12′′ × 12′′ in our lab,even larger with industry tools), thus resulting in low costRDL wiring for high-density interposer applications. Such atechnology extends the capability of current organic packagingprocesses.

ACKNOWLEDGMENT

The authors would like to thank to R. Shafer and M. Broas,Georgia Institute of Technology, for their experimentalsupport.

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[6] E. D. Blackshear et al., “The evolution of build-up package technologyand its design challenges,” IBM J. Res. Develop., vol. 49, pp. 641–661,Jul./Sep. 2005.

[7] F. Liu, V. Sundaram, B. Wiedenman, and R. Tummala, “Advances inhigh density interconnect substrate and printed wiring board technology,”in Proc. 6th Int. Conf. Electron. Packag. Technol., Aug./Sep. 2005,pp. 307–313.

[8] K. Yamanaka, K. Kobayashi, K. Hayashi, and M. Fukui, “Materials,processes, and performance of high-wiring density buildup substratewith ultralow-coefficient of thermal expansion,” IEEE Trans. Compon.Packag. Technol., vol. 33, no. 2, pp. 453–461, Jun. 2010.

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[11] M. Ishida, “APX (advanced package X)—Advanced organic technol-ogy for 2.5D interposer,” in Proc. IEEE Electron. Compon. Technol.Conf. (ECTC), 2014.

[12] M. C. Souter, “Next-generation laser structuring method for higherdensity packages,” Chip Scale Rev., vol. 42, no. 3, pp. 42–45, 2014.

[13] Y. Suzuki, Y. Takagi, V. Sundaram, and R. Tummala, “Thin poly-mer dry-film dielectric material and a process for 10 μm interlayervias in high density organic and glass interposers,” in Proc. IEEE64th Electron. Compon. Technol. Conf. (ECTC), Orlando, FL, USA,May 2014, pp. 1427–1432.

[14] S. Ehrler, R. Mayer, W. Olbrich, and M. Roesch, “High complexityPCB’s for enhanced SMT and bare chip assembly applications,” inProc. 19th IEEE/CPMT Electron. Manuf. Technol. Symp., Oct. 1996,pp. 162–166.

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Yuya Suzuki received the B.S. and M.S. degreesin applied chemistry from the University of Tokyo,Tokyo, Japan, in 2005 and 2007, respectively. He iscurrently pursuing the Ph.D. degree with the Depart-ment of Materials Science and Engineering.

He joined Zeon Corporation, Tokyo, in 2007, asa Research Engineer. He is currently with the 3-DPackaging Research Center, Georgia Institute ofTechnology, Atlanta, GA, USA. His research is thedevelopment of glass interposer and passive embed-ded RF module using low-loss polymer material. His

current research interests include polymer synthesis, polymer processing, andorganic–inorganic hybrid materials.

Ryuta Furuya received the B.S. and M.S. degrees inphysics from the University of Tokyo, Tokyo, Japan,in 2010 and 2012, respectively.

He joined Ushio Inc., Tokyo, in 2012, as aResearch Engineer. He is currently with the 3-DPackaging Research Center, Georgia Institute ofTechnology, Atlanta, GA, USA, as a VisitingEngineer. His recent research was the develop-ment of panel base process for 2.5-D glass/organicinterposer. His current research interests includeprojection lithography optics, opto-electronics, and

microelectromechanical systems packaging.

200 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

Venky Sundaram received the B.S. degree fromIIT Bombay, Mumbai, India, and the M.S. andPh.D. degrees in materials science and engineeringfrom the Georgia Institute of Technology, Atlanta,GA, USA.

He is currently the Director of Research andIndustry Relations with the 3-D Systems PackagingResearch Center, Georgia Institute of Technology.He is the Program Director of the Low Cost GlassInterposer industry consortium with more than 25active global industry members. He is a globally

recognized expert in packaging technology and the Co-Founder of JacketMicro Devices, an RF/wireless start-up acquired by AVX. He has authoredover 100 publications and holds over 15 patents. His current research inter-ests include system-on-package technology, 3-D packaging and integration,ultrahigh-density interposers, embedded components, and systems integrationresearch.

Dr. Sundaram was a recipient of several best paper awards. He is theCo-Chairman of the IEEE Components, Packaging and Manufacturing Tech-nology Society Technical Committee on High Density Substrates. He is on theExecutive Council of the International Conference and Exhibition on DevicePackaging as the Director of Education Programs.

Rao R. Tummala (F’93) received the B.S. degreefrom IIT Bombay, Mumbai, India, and thePh.D. degree from the University of Illinois atUrbana-Champaign, Champaign, IL, USA.

He was an IBM Fellow, pioneering the first plasmadisplay and multichip electronics for mainframesand servers. He is currently a Distinguished andEndowed Chair Professor and the Founding Directorof NSF ERC with the Georgia Institute of Technol-ogy, Atlanta, GA, USA, pioneering Moore’s Lawfor System Integration. He has authored about 500

technical papers, and holds 74 patents and inventions. He authored thefirst modern book entitled Microelectronics Packaging Handbook, the firstundergraduate textbook entitled Fundamentals of Microsystems Packaging,and the first book Introducing the System-On-Package Technology.

Prof. Tummala is a member of the National Academy of Engineering.He was a recipient of many industry, academic, and professional societyawards, including the Industry Week’s Award for improving U.S. compet-itiveness, the IEEE’s David Sarnoff Award, the International Microelec-tronics Assembly and Packaging Society’s (IMAPS) Dan Hughes Award,the Engineering Materials Award from ASM, and the Total Excellence inManufacturing Award from SME. He received the Distinguished AlumniAwards from the University of Illinois at Urbana-Champaign, the IndianInstitute of Science, Bangalore, India, and Georgia Tech. He was also arecipient of the Technovisionary Award from the Indian SemiconductorAssociation and the IEEE Field Award for contributions in electronics systemsintegration, and cross-disciplinary education in 2011. He was the Presidentof the IEEE Components, Packaging and Manufacturing Technology Societyand the IMAPS.