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  • 194 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

    Demonstration of 10-μm Microvias in Thin Dry-Film Polymer Dielectrics for

    High-Density Interposers Yuya Suzuki, Ryuta Furuya, Venky Sundaram, and Rao R. Tummala, Fellow, IEEE

    Abstract— This paper describes the demonstration of 10-µm diameter interlayer vias with 3.5-µm wide re-distribution layer copper wiring in a unique dry-film polymer dielectric, ZEONIF ZS100 (ZS100), suitable for panel-based high-density organic and glass interposers. The uniqueness of polymer dielectric includes low dielectric constant, low dielectric loss, low moisture uptake, and low surface roughness. The dry-film polymer dielectric was laminated on thin and low coefficient of thermal expansion organic or glass cores using double-side vacuum lamination processes. The ultrasmall microvias were drilled with 248-nm KrF excimer laser. Metallization by electroless and electrolytic copper plating successfully achieved formation of fully filled vias and copper traces simultaneously without any chemical– mechanical polishing. The processes demonstrated in this paper enable interposers with much finer bump pitch than current organic package technology. In addition, the processes can be scaled to large panels leading to lower cost than the previous work in fine pitch Si interposers fabricated through back-end- of-line wafer processes.

    Index Terms— Excimer laser, fine pitch via, fine pitch wiring, microvia, thin dielectric film.

    I. INTRODUCTION

    GROWING demand for high-speed electronic systemshas driven the need for ultrahigh density wiring to interconnect two or more ICs either in vertical direction such as by 3-D stack of ICs with through silicon via or in hor- izontal direction by 2.5-D interposers. Such ultrahigh multi- layer wiring for 2.5-D interposers requires ultrasmall diameter interlayer microvias. Silicon interposers have been developed and commercialized to meet such demands using back-end-of- line processes using silicon dioxide or nitride dielectric layers with submicrometer lithographic lines and vias by damascene or dual-damascene processes [1], [2]. Silicon interposers have

    Manuscript received September 5, 2014; revised November 17, 2014; accepted December 12, 2014. Date of publication January 21, 2015; date of current version February 3, 2015. This work was supported by the U.S. Department of Commerce under Grant BS123456. Recommended for publication by Associate Editor J. J. Liu upon evaluation of reviewers’ comments.

    Y. Suzuki is with the 3D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332 USA, and also with the Research and Develop Center, Zeon Corporation, Kawasaki 210-9507, Japan (e-mail: ysuzuki3@mail.gatech.edu).

    R. Furuya is with Ushio Inc., Tokyo 100-8150, Japan (e-mail: rfuruya3@mail.gatech.edu).

    V. Sundaram and R. R. Tummala are with the 3D Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: vs24@mail.gatech.edu; rao.tummala@ece.gatech.edu).

    Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

    Digital Object Identifier 10.1109/TCPMT.2014.2382339

    also been fabricated with photosensitive dielectric materials for wafer level packaging applications to achieve below 10-μm vias [3], [4]. Shinko, for example, has applied liquid pho- tosensitive processes to demonstrate 2-μm lines and 10-μm diameter vias [5]. Since these processes are single sided and designed for small 300-mm wafers, these interposers tend to be expensive. In contrast, organic packaging technology provides a lower cost approach with large panel sizes of 500 mm, utilizing thin dry-film build-up polymer dielectric materials, yielding 8× more packages than from 300-mm wafers [6]. However, fabrication of small microvias at fine pitch and registration of these vias from layer to layer are two barriers to high-density interconnections in organic and other packages. Current organic package manufacturing technol- ogy is at 15-μm wiring with 40–50-μm microvias, using CO2 laser drilling and semi-additive process (SAP). Limiting factors in reducing via diameters include long wavelength (10.2 and 10.6 μm) and large CO2 laser beam focus (60–70 μm). Recent advances in packaging processes such as SAP and Nd-YAG lasers led to the demonstration of 9-μm lithography and 25-μm microvias [7]. Kyocera has demon- strated high density organic interposers with 8 μm line lithography and 25 μm dia. micro-vias drilled with 266 nm Nd-YAG laser [8]. Kyocera recently achieved even smaller, 20 μm micro-vias, by optimization of the Nd-YAG laser parameters. To achieve even smaller dimensions, new advances have been proposed and reported. Atotech and Amkor, for example, have developed Via2

    processes to demonstrate 10-μm line features with trench filling processes using excimer laser and copper plating processes [16], [17]. Fujikura reported one of the most advanced trench circuit technologies to demonstrate 2-μm linewidth and 10-μm microvia diameter [18]. However, trench filling processes require an expensive chemical– mechanical polishing, thus limiting their applicability to large panels.

    This paper reports advances to form 10-μm diameter microvias in 10-μm thick polymer build-up dry films to apply to large panel manufacturing. Table I shows a summary of microvia hole formation processes in thin film dielectric materials. Laser drilling processes have been widely used to form microvia openings because laser processes can make microvias in various dielectric materials, enabling wider mate- rial selection. Conventional serial-laser drilling, such as CO2 and Nd-YAG laser processes have difficulty in making small

    2156-3950 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

  • SUZUKI et al.: DEMONSTRATION OF 10-μm MICROVIAS IN THIN DRY-FILM POLYMER DIELECTRICS 195

    TABLE I

    VIA FORMATION IN FILM MATERIAL BY VARIOUS METHODS

    size vias especially below 15 μm, because of the thermal damage they cause. In addition, these serial processes can create only single via at a time, which limits the throughput. In contrast, excimer laser is compatible with mask projection processes, which enables formation of multiple vias simulta- neously. This ability to form multiple vias at the same time is beneficial for high throughput and for registration between vias. Furthermore, excimer lasers have a potential to provide the smallest vias because of minimum thermal damage. In this paper, the reported research in [13] has been extended and in addition, a detailed analysis of the influence of via opening size in filled plating processes is implemented. As a result, successful demonstration of ultrasmall microvias and copper wirings layers has been achieved. Section I describes the thin polymer dry-film material and lamination processes. Section II discusses the ultrasmall via formation by KrF excimer laser processes. Section III illustrates the method for via metalliza- tion by electroless and electrolytic plating processes. Finally, demonstration of fine pitch microvia and wiring is described in Section IV as the conclusion. The processes developed in this paper are aimed at panel-based processing to form the basis of 50-μm bump pitch re-distribution layer (RDL) wiring in organic and glass interposers.

    II. DIELECTRIC MATERIAL AND PROCESS

    A. Polymer Dielectric Material

    Polymer dielectrics must meet a variety of electrical, thermal, mechanical, and chemical properties. In addition, it must be easily processable with an excellent adhesion to copper and other substrate materials. The ZEONIF ZS100 (ZS100) polymer dry film [19] was selected based on meeting these requirements, as the RDL build-up material in this paper. It is a low loss material and is compatible with SAPs to form copper seed layers with smooth interface. In addition, multilayer RDL structure formation is capable of using ZS-100 because it has high flow during lamination process and microvia can be drilled with a variety of laser processes [20], [21]. Properties of the fully cured ZS100

    TABLE II

    PROPERTIES OF POLYMER (ZS100) USED IN THIS PAPER

    Fig. 1. Difference in surface roughness in ZS100 and existing material.

    polymer dielectric material are summarized in Table II. It has both a low dielectric constant (Dk) and a low electrical loss (Df), which are beneficial for high-speed transmission. In addition, its low moisture absorption contributes to high reliability of the package, especially when the package gets thinner. Other outstanding advantage is its strong chemical bond to electroless plated copper seed layers with a very low surface roughness (Ra < 100 nm) (Fig. 1). This extremely smooth surface is beneficial to form fine line wiring resulting in less copper conductor undercut in forming 3-μm line routing structures, as shown in Fig. 2 [22].

  • 196 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 2, FEBRUARY 2015

    Fig. 2. Fine pitch 3-μm routing structures on ZS100.

    B. Dielectric Film Formation

    The 10-μm thick polymer dry films were laminated on both sides of the copper clad FR-4 core laminate by vacuum lamination at 100 °C. The copper surfaces of copper clad laminate were roughened by standard chemical treatments before the lamination process to enhance adhesion. These panels were hot pressed for 90 s at 3 MPa to planarize the surface of the dielectric. After lamination, the samples were thermally cured in an oven