A Sub-100μW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Applications

Shu-Yu Hsu1, Yingchieh Ho2, Yuhwai Tseng2, Ting-You Lin2, Po-Yao Chang1, Jen-Wei Lee1, Ju-Hung Hsiao1, Siou-Ming Chuang2, Tze-Zheng Yang2, Po-Chun Liu1, Ten-Fang Yang3, Ray-Jade Chen4, Chauchin Su2, Chen-Yi Lee1

1Dept. of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan 2Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu, Taiwan

3Taipei Medical University Hospital, 4Wan Fang Hospital, Taipei, Taiwan

Abstract A multi-functional cardiac signal processor (CSP) with integrated

sensor interfaces is designed for mobile healthcare applications, especially for heart activity diagnosis in different phases. Applying dedicated processing engines, the CSP extracts critical cardiac signal features based on compressed data with 90% storage reduction, while keeping the data network secure. Implemented in 90nm CMOS, the CSP consumes 22.6μW to 46.5μW at 0.5/1.0V in different configurations. Besides, the 10.2μW biopotential and 11.4μW capacitive sensor interfaces further enhance the system functionality.

Introduction The promising mobile healthcare applications record the user’s

vital signals via wireless communications. In such applications, the digital processor is applied with sensors for extended observation duration, timely reaction, or user privacy protection. Nevertheless, the previous solutions consume too much power [1] or only provide limited functionality [2]. A duty-cycled processor is power efficient with high computational capability [3]; however, the input data buffer becomes the power bottleneck for channel expansions. Moreover, no sensor interface is integrated. Accordingly, this work proposes a memory compressed 1-4channel cardiac signal processor (CSP) with sensor interfaces for electrocardiogram (ECG), vectorcardiogram (VCG) and phonocardiogram (PCG) processing. The additional channel monitors the electrical or mechanical heart activities in different phases and provides more information for improved diagnosis/analysis quality. Fig. 1 describes the CSP target scenario with different configurations to support both low power monitoring and high quality diagnosis.

CSP System Architecture Fig. 2 presents the proposed CSP architecture. The digital processor

is implemented based on SW/HW co-worked and duty-cycled approaches to obtain both power efficiency and system flexibility [3]. This includes a 32-bit AndesCore N9 RISC general purpose processor (GPP) with duty-cycled clock generator (DCCG), and hard-wired adaptive compression engine (ACE), feature extraction engine (FEE) and the security engine (SE). The sensor interfaces would be discussed later.

Fig. 3(a) shows the processing flow for cardiac feature extraction. Using ACE in data queuing stage, the required input buffer size for successive processing is reduced by 25% (PCG) to 90% (ECG/VCG) with distortion <1%. The four-level adaptive sampling compresses the low variation signal, which is detected by the min-max deviation [3] within channel buffer of 16 samples. As the buffer sizes are reduced, the small size SRAM are replaced by the voltage scalable (0.5V) registers with 40% power reduction. In addition, the multichannel compression is done by time-multiplexing with reused hardware. Instead of pre-allocating registers in data path, the time-multiplexed approach benefits in scalability to various channel amounts.

Loading from asynchronous buffer, the FEE decomposes cardiac signal into 5 dyadic wavelet scales based on the compressed data. Temporal resolution is maintained using algorithm a`trous [4], and the search kernel is applied for signal delineation. Fig. 3(b) lists that the sensitivity of critical ECG/VCG fiducial point extraction (P, QRSon, R, QRSend, T waves) is still over 99% using compressed data

with selective recovery circuits. The R peak detection is even improved thanks to the inherent filtering. And the PCG events (S1 and S2) are identified after obtaining the ECG fiducial points. According to the prescriptions, the GPP would extract more signal features or directly issue an abnormal classification, based on the FEE results. Besides, the classified alarm and activity level using selected features can be feedback to adjust the system configurations.

Fig. 4 shows the SE with an AES-128, and a 192-bit GF(p)/GF(2n) dual-field elliptic curve crypto processor (DF-ECCP) [5]. Compared with [3], the proposed SE is 15× faster and is compatible to IEEE 802.15.6 [6] with higher security level. Besides, to counteract the power-analysis attacks in continuous recording environment, a hybrid ring oscillator based true random number generator masks the AES key information and provides sequences for randomized Montgomery domain in DF-ECCP. Fig. 5 shows the protected DF-ECCP key is not disclosed even 106 records are analyzed.

CSP Sensor Interfaces One channel biopotential sensor interface (BSI) and capacitive

sensor interface (CSI) are integrated. Fig. 6 depicts the BSI for cardiac signal acquisition. The instrument amplifier (IA) and programmable gain amplifier (PGA) rejects the differential electrode offset, common mode noise, and flicker noise. This features by chopper-stabilizations, a Gm-C filter and an AC feedback circuits with low noise floor. Moreover, up to 50mV electrode impedance mismatch is cancelled. The overall front-end achieves 40-64dB gain at 0.5V supply and obtains clean ECG with suppressed 60Hz powerline interference.

An 8/12-bit 0.5V SAR-ADC using charge recycling technique [7] is applied for BSI in Fig. 7. The total area is saved by the proposed single side of switchable LSB capacitors. Moreover, a bootstrapped circuit with output swing from 2VDD to –VDD [8] not only enhances the conductance of S/H switch but also reduces the leakage at low voltage. Compared to monotonic SAR-ADC [9], the proposed one saves more than 29% switch energy with max ENOB 11.28-bit and 19fJ/conversion at 100kS/s.

Fig. 8 shows the 7-bit all-digital CSI using capacitive-controlled ring oscillators (CCO) and counters with 2kHz sample rate. The CCO comprises hysteresis inverters and the 5/10MHz base frequency is modulated by sensed capacitance (Cs) changes. The measured CSI detects the electrode connection status. For example, the disconnected electrode with less Cs raises 150kHz CCO frequency, which is reported to turn off the CSP for power saving or to alarm the user.

Implementation Results The CSP is fabricated in a standard 90nm 1P9M CMOS technology.

Low-power techniques are applied including power domain partitions, voltage scaling, and fine-grained clock, power gating. The global supply voltage is scaled to 0.5V except the I/O transfer domain and SRAM. Two-stage duty-cycling is applied to the data queuing stage and signal processing stage with frequency of 100kHz and 25MHz, respectively, where the 25MHz clock is generated from DCCG [3]. Fig. 9 shows the CSP chip photo including digital modules and sensor interfaces with testing considerations. In summary, with 0.25% and 0.02% duty cycle in the two stages, 22.6μW is consumed to perform the single-lead ECG arrhythmia detection. Compared with [3], 12% power is reduced based on the compressed data analysis. Besides, the high quality diagnosis mode extracts the cardiac features and activity levels with 46.5μW power, which is 48% lower than without using ACE. To further enhance the CSP functionality, the 10.2μW BSI and 11.4μW CSI are integrated with the least power overhead.

The authors would like to thank UMC for the test chip fabrication, Andes Technology for the AndesCore N9 license, and the National Science Council of Taiwan for grant support NSC99-2220-E-009-068.

978-1-4673-0849-6/12/$31.00 ©2012 IEEE 2012 Symposium on VLSI Circuits Digest of Technical Papers 156

References [1] A.C.-W. Wong, et al., “A 1V, Micropower System-on-Chip for Vital-Sign

Monitoring in Wireless Body Sensor Networks, “ ISSCC, Feb. 2008. [2] S. C. Jocke, et al, “A 2.6-μW Sub-threshold Mixed-signal ECG SoC,” Symp.

on VLSI Circuits, pp. 60-61, Jun. 2009. [3] S. Y. Hsu, et al, "A Micropower Biomedical Signal Processor for Mobile

Healthcare Applications," A-SSCC, pp. 301-304, Nov. 2011. [4] J. P. Martínez, et al, “A Wavelet-based ECG Delineator: Evaluation on

Standard Databases,” IEEE TBME, vol. 51, no.4, pp. 570-581, Apr. 2004. [5] J. W. Lee, et al., “A 521-bit Dual-Field Elliptic Curve Cryptographic

Processor with Power Analysis Resistance,” ESSCIRC, Sep. 2010. [6] IEEE 802.15 WPAN™ Task Group 6 (TG6) Body Area Networks. [7] B. P. Ginsburg, et al, “An Energy-Efficient Charge Recycling Approach for

a SAR Converter with Capacitive DAC,” ISCAS, May 2005. [8] Y. Ho, et al., “A 0.2-0.6 V Ring Oscillator Design Using Bootstrap

Technique,” A-SSCC, pp. 333-336, Nov. 2011. [9] C. C. Liu, et al., “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor

Switching Procedure,” IEEE JSSC, Apr. 2010.

Fig. 4 The SE architecture with 128-bit AES, 192-bit DF-ECCP and 8-bit ring oscillator based true random number generator

Fig. 5 The measured results of protected/unprotected DF-ECCP key information

Fig. 1 The CSP system overview with multi-configuration modes

Fig. 2 The CSP system architecture and behavior timeline

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(b) Fig. 3 (a) The processing flow and architecture for cardiac feature extractionbased on the compressed data and (b) the extraction results

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Fig. 7 The charge recycling SAR-ADC with energy analysis

Fig. 8 The CSI block diagram and the measured CSI result reflecting the electrode connection status

Fig. 9 The CSP chip photo and the design summary

978-1-4673-0849-6/12/$31.00 ©2012 IEEE 2012 Symposium on VLSI Circuits Digest of Technical Papers 157