18.01.06 J. Jones (Imperial College London), Alt. GCT Mini-Meeting

Source Card Design Status and Plans

J. Jones (Imperial College London), Alt. GCT Mini-Meeting 218.01.06

Overview

Source Card Tasks Separate e/γ from jets Condense 2x68-way SCSI (RCT) 4x1.4Gbit/s optical fibre BC0 sync. checking (compare TTC with BC0 embedded in data) Autocalibrated delay to phase match data on different channels (if required) USB 2.0 interface for diagnostic/testing (borrowed from IDAQ-APVE) Swtiches data between channels to provide ‘split’ information to leaf cards

Extra features On-board temperature/status monitoring Read out either during gaps in data (via concentrator card)…or via USB Data capture from RCT (for debugging) Internal test pattern generation (up to 1024BX) for testing leaf cards, etc… Can (in theory) scale to 2 x required bandwidth (pin-compatible part)

J. Jones (Imperial College London), Alt. GCT Mini-Meeting 318.01.06

Board Layout (Preliminary) 6/8-layer 6U VME form factor USB 2.0 (Cypress SX2) TTCrx & QPLL 2xVHDCI SCSI for RCT input 4xOptical SFP output & SerDes Linear supplies for fast components Switch-mode (TI) for logic

Either: 2 x XC3S1000-4FT256 (~£80) Simpler design Longer latency

Or: 1 x Xilinx Spartan 3 4-8 x Xilinx Coolrunner-II CPLD More complex design Lower Latency

J. Jones (Imperial College London), Alt. GCT Mini-Meeting 418.01.06

Functional Issues (To Be Discussed)

Clock Distribution Direct from QPLL Split by dedicated clock buffer (made by TI) No PLL in splitter to minimise jitter Max skew ~500ps (OK for 80MHz)

SerDes TLK2501 seems like a good choice with bandwidth margin

ECL Termination Scheme Have a version done, but would like to discuss with Wisconsin first Similar to Bristol IM, with a few extra tweaks / options Use same buffers (they have wide common-mode range, +5V to -4V)

J. Jones (Imperial College London), Alt. GCT Mini-Meeting 518.01.06

Source Card Latency RCT->Leaf (Maximum Limit)

Madison Cable (quoted from datasheet)1.5ns/ftAssume 5ft max. length => 1.5x5 = 7.5ns delay

ECL Buffers 2.5ns-6ns (4ns typical)

FPGA/CPLDFPGA (XC3S1000): 5ns in IOBs, at a guess >5ns trace delay = 10nsCPLD (Coolrunner-II): 3.8ns-7.1ns total delay

SerDes38 bit-times@1.6GHz (625ps) = 23.75ns

PCB TrackingAssume 10-inch@300ps/inch = 3ns

Optical Fibre (20m)50ns-75ns?

Estimated Total:7.5+6+(3.8<->10)+23.75+3 = 44.05ns-50.25ns ~ 2BX + 2-3BX

J. Jones (Imperial College London), Alt. GCT Mini-Meeting 618.01.06

Source Card Skew (Maximum Limit)

Madison Cable (quoted from datasheet)

0.025ns/ft maximum

Assume 5ft max. length => 0.025x5 = 0.175ns skew

ECL Buffers

1ns max. (part-part)

FPGA/CPLD

Negligible skew (can be controlled)

SerDes

N/A

PCB Tracking

Can (will) be controlled

Estimated Total:

0.175+1 = 1.75ns << 12.5ns clock

J. Jones (Imperial College London), Alt. GCT Mini-Meeting 718.01.06

Build Plan & Price (Guess)

Schematic

ME

Layout

S. Greenwood (IC) – She’s starting now

Manufacture (awaiting quote from Cemgraft)

Have checked, they’re not too busy a.t.m.

Cemgraft (assembly/parts)

ExceptionPCB (PCB manufacture)

Good experience with complex high-speed boards in the past

18 RCT crates x 6 cables / 2 => 54 cards

Should be < £1000 / card => ~£60,000 for 60 required (with spares)

J. Jones (Imperial College London), Alt. GCT Mini-Meeting 818.01.06

Schedule

Schematic (1-2 months)

Aim to finish ASAP, but I’m kinda busy until 3am… (APVE, SLHC)

Preferrably draft end of January, but definitely end of February

Layout (2 months)

End of February latest

Parts (?)

Critical parts ordered by end of January

Not fancy parts

Should be able to get prototype parts by submission date

Firmware (2 months)

Me & A. Rose? (Some firmware adopted from IDAQ or written now)

Aim to prototype with testing end of March

I suspect this may be optimistic, parts will probably cause delays

March is contingency (leaf card is probably not available by then?)