18 - 322 Fall 2002 Lecture 20 - Carnegie Mellon University

18 - 322 Fall 2002 Lecture 20

Bipolar Junction Transistor (BJT)

• NPN Cross-section and Masks• BJT Notation• Hand Analysis Models• NPN Modes of Operation• Ebers - Moll Model• BJT Inverter• TTL

Chapter 2.4

NPN Transistor Cross-section

NPN Transistor Layout

p

n

p

p

n

BipolarJunctionTransistor (BJT) Notation

Collector

Base

Emitter

n-p-n transistor

n

n

n

n

n

pp B

C C C

B B

EE E

IC

IE

IB

NPN Regions of Operation

V

V BE

BC

Forward Active

Reverse Active

Saturation

Cut-off

NPN Forward Active PolarizationVBE Forward-biased &

VBC Reverse-biased

Base current:IB = IC / βF βF = IC / IB

βF - current gain (~100!)

E C

BElectron Flow(Current in opposite direction)

Common-Emitter Characteristics

B

C

E

VBE

VCE

C I [mA]

3

2

1

0

5

4

7

6

10

9

8

12

11

14

13I = 120µA

B

VCE [V]5.04.03.02.01.0

I = 100µAB

I = 80µAB

I = 60µAB

I = 40µAB

I = 20µAB

Saturation Region C I [mA]

3

2

1

0

5

4

7

6

10

9

8

12

11

14

13I = 120µA

B

VCE [V]5.04.03.02.01.0

I = 100µAB

I = 80µAB

I = 60µAB

I = 40µAB

I = 20µAB

• VBE Forward-biased• VBC Reverse-biased

• No Current Gain relationship.

Hand Analysis Model

VCE

IC

VBE

IB

VBE(on) = 0.7 V VCE(sat) = 0.1 V

IC (active) = βF IBIB = IS (eVbe/Vt -1)

Hand Analysis Example

IC

IE

IB

RC

5V

+-

RB=20kΩ

• RC = 300ΩIB =

IC =

VCE =

Operation Mode:

• RC = 1k ΩIB =

IC =

VCE =

Operation Mode:

βF=1002.7V

BJT Parasitics

• Junction Capacitances:

– Base-Emmitter– Base-Collector

• Excess Base Charge:

– QR when– VBC forward-biased– Must be removed to

switch modes

S

CCS

Cbc

Cbe

QR

QF

NPN Transistor Doping Levels

BE C

nn p

1020

1017cm

-3

2 103

N D N A

Depletion layers

1015

cm-3

N D

2

2 105

cm-3

np Junctions Revisted

• Forward-biased:

– Dominant current: diffusion of majority carriers

• Reverse-biased:

– Drift of minority carriers

NPN Forward Active Polarization

VBE > 0 & VBC < 0

VBE VBCB

E C

nn p

forward-biased

reverse-biased

+-

+ -

Concentration of minority

carriers

NPN Forward Active Polarization

VBE > 0 & VBC < 0

VBE VBCB

E C

nn p

forward-biased

reverse-biased

+-

+ -

Current determined by concentration

of minority carriers

Current determined by concentration

of majority carriers

NPN Forward Active PolarizationVBE > 0 & VBC < 0

VBE VBCB

E C

nn p

forward-biased

+-

+ -

Concentration proportional to

VBE

VTe


VBE VBCB

E C

nn p

reverse-biased

+-

+ -

Concentration proportional to

VBC

VTe


BE C

nn p

Collector current:IC = IS [exp(VBE/VT) -1]

IS - saturation current

Collector current

determined by the slope of the concentration

of minority carriers

(electrons) in the base.

NPN Transistor Reverse ActiveVBE < 0 & VBC > 0

BE C

nn p

forward-biased

reverse-biased

βF > βR

NPN Transistor SaturationVBE > 0 & VBC > 0

BE C

nn p

forward-biased

forward-biased

NPN_Cut-off

BE C

nn p

VBE < 0 & VBC < 0

Ebers-Moll Modelnn

B

C

E

C

B

E

IDC

IDC

DEI

DEI

αF

α R

Ebers - Moll Model

Equations:IDE = IES [exp(VBE/VT) -1]IDC = ICS [exp(VBC/VT) -1]

Typical values:αF = .99 IES = 10-15 AαR = .66 ICS = 10-15 A

BJT Inverter & Fan-Out Analysis

• BJT Inverter

• Voltage Transfer Characteristics

• Logic Level Description

• Fan-Out Analysis

BJT Inverter

= 5 V

in

out

CC

R

R

V

V

V

C

B

10 k Ω

1 kΩ

100 Ω/

10 = 1kΩ

inV = 0 V inV = 5 V

CCV

outV

Base diffusion

NPN BJT Parameters

VBE(on) = 0.7 VVBE(sat) = 0.8 VVCE(sat) = 0.1 V

Forward active mode:• current gain βF = 70

V = +5 V

VOH and VIL

BE C

nn p

outV = 5 V

inV = 0 V

= 5 VCCV

R B

10 k Ω

RC1 k Ω

Q0 cut-off

EBV = 0 V

CB

I B

BI = 0

I C

EBV = 0 - 0.7 V Cut-off

CI = 0

VOH and VIL

Cut-offVout [V]

Vin [V]

5

4

3

2

1

0

0 1 2 3 4 5

VOH

VIL

BP1

0.7 V

VOL

BE C

nn p

outV = 0.1V

inV = 5 V

= 5 VCCV

R B

10 k Ω

RC1 kΩ

Q0

Saturation V = 0.1 V

EBV = 0.7 V

outI B

BI = (5-0.7)/10kΩ = 0.43 mA

I C

CI = I βF = 30 mAB

βF = 70 in Forward Active

outV = 5 - I R = -25 V ?C C

CI < I βF = 30 mAB βF < 70

NOT Forward Active !

VOL

Saturation

Cut-offVout [V]

Vin [V]

5

4

3

2

1

0

0 1 2 3 4 5

VOH

VOL

VIL

BP1

0.7 V

0.1 V

VIH

outV = 0.1V inV = ?

= 5 VCCV

R B

10 k Ω

RC1 kΩ

Q0

Edge of saturation:

EBsV = 0.8 V

I B

BI = ((5-0.1)/1kΩ)/70 = 70 µA

I C

βF = 70

in

V = V + I R = 0.8 + 0.7B B EBs

V = 1.5 V

outV = 0.1V

VIH

Saturation

Cut-offVout [V]

Vin [V]

5

4

3

2

1

0

0 1 2 3 4 5

VOH

VOL

VIL VIH

BP1

BP2

0.7 V

0.1 V

1.5 V

Transition Region

outV = 5.0 - 0.1 V inV = 0.7 - 1.5V

= 5 VCCV

R B

10 k Ω

RC1 kΩ

Q0

B

CI = I βFB

Forward Active !

I = (V - 0.7)/R in B

outV = V - I R C C CC

Transition Region:Load Line Analysis

V = 0.7 - 1.5V

B

CI = I βFB

I = (V - 0.7)/R in B

outV = V - I R C C CC

in

CI [mA]

3

2

1

0

5

4

7

6

10

9

8

12

11

14

13I = 120µAB

VCE [V]5.04.03.02.01.0

I = 100µAB

I = 80µAB

I = 60µAB

I = 40µAB

I = 20µAB

BI = (1.5 - 0.7)/ 10kΩ = 80 µΑ

Voltage Transfer Characteristic

Saturation

Forward Active

Cut-offVout [V]

Vin [V]

5

4

3

2

1

0

0 1 2 3 4 5

VOH

VOL

VIL VIH

BP1

BP2

Voltage Transfer Characteristic

Vout [V]

Vin [V]

5

4

3

2

1

0

0 1 2 3 4 5

VOH

VOL

VIL VIH

BP1

BP2

• Transition Width:TW= VIH - VIL = .8 V

• High Noise Margin:NMH = VOH - VIH = 3.5 V

• Low Noise Margin:NML = VIL -VOL = .6 V

• Logic Swing:LS = VOH - VOL = 4.9 V

Inverter Fan-Out

outV

inV

= 5 VCCV

RB

10 k Ω

RC1 k Ω

RB

10 k Ω

RC1 k Ω

R B

10 k Ω

RC1 kΩ

Q0 Q1

QN

inV = 0

RB

n

Inverter Fan-Out• LOAD =1 VOH = 4.6 V

outV = 4.6 V

inV = 0.1 V

= 5 VCCV

RB

10 k Ω

RC1 kΩ

R B

10 k Ω

RC1 k Ω

Q0 Q1cut-offsaturation

RB

RB

RC

+V = ( V CC - 0.8 ) + 0.8 =

10

10 1 +( 5.0 - 0.8 ) + 0.8 = 4.61 V

out

Equivalent Circuit

VOH = ?

outV

inV

= 5 VCCV

R /NB

RB

10 k Ω

RC1 k Ω

Q0 V BE(sat)

R / N B

R /N B

RC

+V = ( V CC - 0.8 ) + 0.8 =

10 /10 10 /10 1 +

( 5.0 - 0.8 ) + 0.8 = 2.9 V

out

Maximum Number of Load Gates: VOH = VIH

outV

inV

= 5 VCCV

R /NB

R B

10 k Ω

RC1 k Ω

Q0 V BE(sat)

VOH = ?

VIH = ?

N = ?

R / N B

R /N B

RC

+V = ( V CC - 0.8 ) + 0.8

10 /N 10 /N 1 +

( 5.0 - 0.8 ) + 0.8 = 1.5 V

out

Transistor-Transistor Logic (TTL)

• Disadvantages of TTL gates:• Large # of components, area --> VLSI not

feasible• Large power consumption• Saturated transistors in either high or low state

• Large propagation times

• Advantage:• Can drive large capacitive loads since large

output currents available

TTL Inverter= 5 VCCV

R 4130 Ω

Q1 Q

2

Q3

D1

A

R 14 k Ω

R31.6 k Ω

R 21 k Ω

Q4

INPUT STAGE OUTPUT STAGEPHASE-SPLITTERor

LEVEL-SHIFT

TTL NAND Gate= 5 VCCV

R 4130 Ω

Q2

Q3

D1

R 14 k Ω

R31.6 k Ω

R 21 k Ω

Q4

INPUT STAGE OUTPUT STAGEPHASE-SPLITTERor

LEVEL-SHIFT

Q1AA

Q1B

B

Multi-Emitter Transistor

pn

E1 E2 B C

E1

E2

B

C

E1

E2

B

C

18 - 322 Fall 2002 Lecture 20 - Carnegie Mellon University

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