Preliminary data

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

December 2011 Doc ID 022595 Rev 1 1/20

20

TDA7498E

160-watt + 160-watt dual BTL class-D audio amplifier

Features■ 160-W + 160-W output power at

THD = 10% with RL = 4 Ω and VCC = 36 V

■ 1 x 220 W output power mono parallel BTL at THD = 10% with RL = 3 Ω and VCC = 36 V

■ Wide-range single-supply operation (14 - 36 V)

■ High efficiency (η = 85%)

■ Parallel BTL function using the MODE pin

■ Four selectable, fixed gain settings of nominally 23.8 dB, 29.8 dB, 33.3 dB and 35.8 dB

■ Differential inputs minimize common-mode noise

■ Standby and mute features

■ Smart protection

■ Thermal overload protection

■ Small offset less than 20 mV

DescriptionThe TDA7498E is a dual BTL class-D audio amplifier with a single power supply designed for home systems and active speaker applications.

It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink.

PowerSSO36with exposed pad up

Table 1. Device summary

Order code Operating temp. range Package Packaging

TDA7498E 0 to 70 °C PowerSSO36 (EPU) Tube

TDA7498ETR 0 to 70 °C PowerSSO36 (EPU) Tape and reel

www.st.com

Contents TDA7498E

2/20 Doc ID 022595 Rev 1

Contents

1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 For RL = 4 Ω, stereo configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 For RL = 3 Ω, mono BTL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 Stereo and mono BTL operation selection using the MODE pin . . . . . . . 16

5.2 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3 Smart protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

TDA7498E List of figures

Doc ID 022595 Rev 1 3/20

List of figures

Figure 1. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 2. Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 3. Test circuit stereo application and mono BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 4. Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 5. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 6. THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 7. FFT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 8. Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 9. Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 10. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 11. THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 12. PowerSSO36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Device block diagram TDA7498E

4/20 Doc ID 022595 Rev 1

1 Device block diagram

Figure 1 shows the block diagram of one of the two identical channels of the TDA7498E.

Figure 1. Internal block diagram (showing one channel only)

TDA7498E Pin description

Doc ID 022595 Rev 1 5/20

2 Pin description

2.1 Pinout

Figure 2. Pin connections (top view, PCB view)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

28

29

30

31

32

33

34

35

36

19

20

21

22

23

24

25

26

27

VSS SUB_GND

OUTPB

OUTPB

PGNDB

PGNDB

PVCCB

PVCCB

OUTNB

OUTNB

OUTNA

OUTNA

PVCCA

PVCCA

PGNDA

PGNDA

OUTPA

OUTPA

PGNDVDDPW

STBY

MUTE

INPA

INNA

ROSC

SYNCLK

VDDS

SGND

DIAG

SVR

GAIN

MODE

INPB

INNB

VREF

SVCC

EP, exposed padConnect to ground

Pin description TDA7498E

6/20 Doc ID 022595 Rev 1

2.2 Pin list

Table 2. Pin description list

Number Name Type Description

1 SUB_GND PWR Connect to the frame

2,3 OUTPB O Positive PWM for right channel

4,5 PGNDB PWR Power stage ground for right channel

6,7 PVCCB PWR Power supply for right channel

8,9 OUTNB O Negative PWM output for right channel

10,11 OUTNA O Negative PWM output for left channel

12,13 PVCCA PWR Power supply for left channel

14,15 PGNDA PWR Power stage ground for left channel

16,17 OUTPA O Positive PWM output for left channel

18 PGND PWR Power stage ground

19 VDDPW O3.3-V (nominal) regulator output referred to ground for power stage

20 STBY I Standby mode control

21 MUTE I Mute mode control

22 INPA I Positive differential input of left channel

23 INNA I Negative differential input of left channel

24 ROSC O Master oscillator frequency-setting pin

25 SYNCLK I/O Clock in/out for external oscillator

26 VDDS O3.3-V (nominal) regulator output referred to ground for signal blocks

27 SGND PWR Signal ground

28 DIAG O Open-drain diagnostic output

29 SVR O Supply voltage rejection

30 GAIN I Gain setting input

31 MODE I Enables stereo or mono BTL mode of operation

32 INPB I Positive differential input of right channel

33 INNB I Negative differential input of right channel

34 VREF O Half VDDS (nominal) referred to ground

35 SVCC PWR Signal power supply

36 VSS O 3.3-V (nominal) regulator output referred to power supply

- EP - Exposed pad for heatsink, to be connected to ground

TDA7498E Electrical specifications

Doc ID 022595 Rev 1 7/20

3 Electrical specifications

3.1 Absolute maximum ratings

3.2 Thermal data

3.3 Recommended operating conditions

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC supply voltage for pins PVCCA, PVCCB, SVCC 40 V

VIVoltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN, MODE

-0.3 to 4.0 V

Tj Operating junction temperature 0 to 150 °C

Top Operating ambient temperature 0 to 70 °C

Tstg Storage temperature -40 to 150 °C

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit

Rth j-case Thermal resistance, junction to case - 3.0 °C/W

Table 5. Recommended operating conditions

Symbol Parameter Min Typ Max Unit

VCC Supply voltage for pins PVCCA, PVCCB, SVCC 14 - 36 V

Tamb Ambient operating temperature 0 - 70 °C

Electrical specifications TDA7498E

8/20 Doc ID 022595 Rev 1

3.4 Electrical specificationsUnless otherwise stated, the values in the table below are specified for the conditions: VCC = 36 V, RL = 4 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 23.6 dB Tamb = 25 °C.

Table 6. Electrical specifications

Symbol Parameter Condition Min Typ Max Unit

Iq Total quiescent current No LC filter, no load - 60 mA

IqSTBY Quiescent current in standby - - 1 µA

VOS Output offset voltage Vi = 0 Av = 23.6 dB, no load

-20 - 20 mV

IOCP Overcurrent protection threshold RL = 0 Ω 10 11 14 A

TjJunction temperature at thermal shutdown

- 140 150 160 °C

Ri Input resistance Differential input 69 - kΩ

VUVP Undervoltage protection threshold - - - 8 V

RdsON Power transistor on resistanceHigh side - 0.15 -

ΩLow side - 0.15 -

Po Output powerTHD = 10% - 160 -

WTHD = 1% - 125 -

PoParallel BTL (mono) output power, RL = 3 ohm, Vcc = 36 V

THD = 10% - 220 -W

THD = 1% - 170 -

η Efficiency - 85 - %

THD Total harmonic distortion Po = 1 W - 0.05 - %

GV Closed-loop gain

GAIN0 < 0.25*VDD 23.8

dB0.25*VDD < GAIN < 0.5*VDD 29.8

0.5*VDD < GAIN < 0.75*VDD 33.3

GAIN > 0.75*VDD 35.8

ΔGV Gain matching - -1 - 1 dB

CT Crosstalk f = 1 kHz, Po = 1 W 50 60 - dB

Vn Total output noise

Inputs shorted and to Ground A curve

231 µV

Inputs shorted and to Ground f = 20 Hz to 20 kHz

400 µV

SVRR Supply voltage rejection ratiofr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 µF

- 55 - dB

Tr, Tf Rise and fall times - - 35 - ns

fSW Switching frequency Internal oscillator 240 310 400 kHz

fSWR Output switching frequency rangeWith internal oscillator by changing Rosc(1) 240 - kHz

TDA7498E Electrical specifications

Doc ID 022595 Rev 1 9/20

VinH Digital input high (H)-

2.0 - -V

VinL Digital input low (L) - - 0.8

Function mode

Standby & mute & play

STBY < 0.5 V, MUTE = X StandBy

STBY > 2.5 V ; MUTE < L Mute

STBY > 2.5 V, MUTE > H Play

AMUTE Mute attenuation VMUTE < L, VSTBY = H - 75 - dB

1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 3)

Table 6. Electrical specifications (continued)

Symbol Parameter Condition Min Typ Max Unit

Electrical specifications TDA7498E

10/20 Doc ID 022595 Rev 1

3.5 Test circuit

Figure 3. Test circuit stereo application and mono BTL mode

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IN S

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23.6

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34V

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7498

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R1

47k

R7

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C6

100n

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R4

120k R2

33k

R8

6.8k

C26 1uF

C10

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L3 L1 L2

C17 10uF

10V

C16

10uF

10V

D1

18V

J4

C30

1uF

C31

1uF

R15

8RC

28

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F

R16 8R

C24

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F

R17 8R

C18

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F

R18 8R

C22

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F

SY

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24 13

J1

R10

100k

R11

100k R

1210

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J11

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J3

R3

39K

C8

100n

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R9

180K 1

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R13

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Characterization curves TDA7498E

11/20 Doc ID 022595 Rev 1

4 Characterization curves

Unless otherwise stated, measurements were made under the following conditions:

Vcc = 36 V, f = 1 kHz , GV = 23.6 dB, Rosc = 39 kΩ, Cosc = 100 nF, Tamb = 25 °C.

4.1 For RL = 4 Ω, stereo configuration

Figure 4. Output power vs. supply voltage

Characterization curves TDA7498E

12/20 Doc ID 022595 Rev 1

Figure 5. THD vs. output power

Figure 6. THD vs. frequency

TDA7498E Characterization curves

Doc ID 022595 Rev 1 13/20

Figure 7. FFT performance

Figure 8. Crosstalk vs. frequency

Characterization curves TDA7498E

14/20 Doc ID 022595 Rev 1

4.2 For RL = 3 Ω, mono BTL configuration

Figure 9. Output power vs. supply voltage

TDA7498E Characterization curves

Doc ID 022595 Rev 1 15/20

Figure 10. THD vs. output power

Figure 11. THD vs. frequency

Application information TDA7498E

16/20 Doc ID 022595 Rev 1

5 Application information

5.1 Stereo and mono BTL operation selection using the MODE pinThe TDA7498E can be used in stereo applications or mono BTL applications. Connecting the MODE pin to the VDDS pin configures the device in mono BTL. The output of the two channels can be paralleled. When the MODE pin is connected to ground or floating (pulled down internally) the device works as a stereo amplifier.

5.2 Gain settingThe gain of the TDA7498E is set by GAIN (pin 30).

5.3 Smart protectionTo avoid dynamic impedance drop, two overcurrent thresholds are set. The first threshold is for the overcurrent limit. The device limits the output current to the first threshold but does not shut down the PWM outputs.

If the device is shorted and at least one of the two output currents reaches the second threshold, the device is shut down immediately. The device will recover automatically when the fault is removed from the BTL outputs.

Table 7. Gain settings

GAIN0 Total Gain Application suggestion

VGAIN < 0.25*VDDS 23.6 dB GAIN pin connected to SGND

0.25*VDDS < VGAIN < 0.5*VDDS 29.6 dB Rc10 = Rc11= Rc12 = 100 K max

0.5*VDDS < VGAIN < 0.75*VDDS 33.1 dB Rc10 = Rc11 = Rc12 = 100K max

VGAIN > 0.75*VDDS 35.6 dB GAIN pin connected to VDDS

TDA7498E Package mechanical data

Doc ID 022595 Rev 1 17/20

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

The TDA7498E comes in a 36-pin PowerSSO package with exposed pad up.

Figure 12 shows the package outline and Table 8 gives the dimensions.

Table 8. PowerSSO36 EPU dimensions

SymbolDimensions in mm Dimensions in inches

Min Typ Max Min Typ Max

A 2.15 - 2.45 0.085 - 0.096

A2 2.15 - 2.35 0.085 - 0.093

a1 0 - 0.10 0 - 0.004

b 0.18 - 0.36 0.007 - 0.014

c 0.23 - 0.32 0.009 - 0.013

D 10.10 - 10.50 0.398 - 0.413

E 7.40 - 7.60 0.291 - 0.299

e - 0.5 - - 0.020 -

e3 - 8.5 - - 0.335 -

F - 2.3 - - 0.091 -

G - - 0.10 - - 0.004

H 10.10 - 10.50 0.398 - 0.413

h - - 0.40 - - 0.016

k 0 - 8 degrees - - 8 degrees

L 0.60 - 1.00 0.024 - 0.039

M - 4.30 - - 0.169 -

N - - 10 degrees - - 10 degrees

O - 1.20 - - 0.047 -

Q - 0.80 - - 0.031 -

S - 2.90 - - 0.114 -

T - 3.65 - - 0.144 -

U - 1.00 - - 0.039 -

X 4.10 - 4.70 0.161 - 0.185

Y 4.90 - 7.10 0.193 - 0.280

TD

A7498E

Packag

e mech

anical d

ata

Doc ID

022595 Rev 1

18/20

Figure 12. PowerSSO36 EPU outline drawing

h x 45°

TDA7498E Revision history

Doc ID 022595 Rev 1 19/20

7 Revision history

Table 9. Document revision history

Date Revision Changes

12-Dec-2011 1 Initial release.

TDA7498E

20/20 Doc ID 022595 Rev 1

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