10Gb/s Ethernet Platform Implementation

Click here to load reader

  • date post

    16-Oct-2021
  • Category

    Documents

  • view

    0
  • download

    0

Embed Size (px)

Transcript of 10Gb/s Ethernet Platform Implementation

Untitled 3.key01
APPLICATIONS
II. XAUI/XGMII - 8 Bytes with 8bits control signals!
Interfaces
!
IV. Avalon MM -A standard address-based read/write interface typical of master-slave connections.
Pin Assignment Matching
Configuration
MAC
λConvert between XGMII and Avalon ST Interfaces λCalculate Checksum λCheck or Append Checksum
λFast/Transparent MAC λ3 clock cycle latency rx λ2 clock cycle latency tx
MAC
CRC-32
Connections!
ST/MM
λProblem: Data is received and transmitted with a bus width of 64 bits of data, MM interface supports only 32 bits with no control signals Problem: Data is received and transmitted with a bus width of 64 bits of data, MM interface supports only 32 bits with no control signals
λSolution for Control λ7a7a7a7a = SOP λ7b7b7b7b = EOP λ7d7d7d7d = escape λ7e7e7e7e = no data λDual Clock FIFO
Challenges/Roadblocks