10GBASE-T Line Signaling
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May 2003 Plato Labs 10GBASE 10GBASE - - T Line Signaling T Line Signaling Joseph N. Babanezhad [email protected] (408)-379-5115 Samir Thosani [email protected] Plato Labs
Transcript of 10GBASE-T Line Signaling
May 2003 Plato Labs
10GBASE10GBASE--T Line Signaling T Line Signaling
Joseph N. [email protected]
(408)-379-5115Samir Thosani
Plato Labs
May 2003 Plato Labs
Analog Front End (AFE) modelAnalog Front End (AFE) modelfor DSP Solutionfor DSP Solution
PSF
HYB
RID
AAFPGA
HYB
RID
AAF PGA
PSF
RecoveredClock
SynthesizedClock
RecoveredClock
1 : 1
UTP
1 : 1
TXADC RXADC
TXADC
May 2003 Plato Labs
• 2 Vp peak-to-peak PAM-M launch signal• Analog differential blocks have only odd non-linearity• Analog blocks are characterized by:
Y = ββββX(1+ααααX2)
• ββββ block gain• αααα 3rd order non-linearity coefficient
Assumptions for AFE Linearity Assumptions for AFE Linearity AnalysisAnalysis
May 2003 Plato Labs
WorstWorst--case Noncase Non--linearity Error (0m)linearity Error (0m)
May 2003 Plato Labs
Combined AFE Non-linearity (7 blocks)
-Vp Vp0
Vp(1 + 7αVp2 + 63α2Vp
4)
Vp
2
Vp
2-Vp(1 + 7α Vp2 + 63 α2Vp
4)
(Accurate PAM5 IN)
X(1 + 7αX2 + 63α2X4)
(Warped PAM5 OUT)
IN
OU
T
May 2003 Plato Labs
AFE Linearity Requirement vs. AFE Linearity Requirement vs. LineLine--SignalSignal
0.43
0.31
1.74
|αααα|Formula
(%)
0.455.742.000PAM-17(Cicada 1/00)
0.3510.003.134PAM-10(Solar Flare)
2.007.002.000PAM-5(Plato Labs)
|αααα|Simulation
(%)
Launch Power (dBm)
Peak-to-Peak (V)
Line Code
May 2003 Plato Labs
WorstWorst--case Noncase Non--linearity Error linearity Error (Normalized (Normalized -- 0m)0m)
May 2003 Plato Labs
Combined AFE Non-linearity (7 blocks normalized)
-Vp Vp0Vp
2
Vp
2-Vp(1 + 7α Vp
2 + 63 α2 Vp4)
(Accurate PAM5 IN)
X(1 + 7αX2 + 63α2 X4)
(Warped PAM5 OUT)
IN
OU
T1 + 7αVp
2 + 63α2 Vp4
1 + 7αVp2 + 63α2 Vp
4
4 16
Vp(1 + 7 α Vp2 + 63 α2 Vp
4)
1 + 7αVp2 + 63α2 Vp
4
4 16
May 2003 Plato Labs
AFE Linearity Requirement AFE Linearity Requirement (Normalized) vs. Line(Normalized) vs. Line--SignalSignal
1.30
1.00
7.10
|αααα|Formula
(%)
2.755.742.000PAM-17(Cicada 1/00)
1.3010.003.134PAM-10(Solar Flare)
6.007.002.000PAM-5(Plato Labs)
|αααα|Simulation
(%)
Launch Power (dBm)
Peak-to-Peak (V)
Line Code
May 2003 Plato Labs
ClassClass--E 4E 4--Connector Channel Model1Connector Channel Model1
May 2003 Plato Labs
Channel Capacity 1Channel Capacity 1
15.5215.4614.75Capacity (Gbps)
-150-150-143NOISE (dBm/Hz)
1005050FEXT Cancellation (dB)
1006565ECHO Cancellation (dB)
1005050NEXT Cancellation (dB)
• Avaya ANEXT model: -60+10 log10( )• No ANEXT Cancellation is considered
f100
May 2003 Plato Labs
Modified ClassModified Class--E 4E 4--Connector Channel Model2Connector Channel Model2
May 2003 Plato Labs
Channel Capacity 2Channel Capacity 2
18.5918.5217.77Capacity (Gbps)
-150-150-143NOISE (dBm/Hz)
1005050FEXT Cancellation (dB)
1006565ECHO Cancellation (dB)
1005050NEXT Cancellation (dB)
• Avaya ANEXT model: -60+10 log10( )• No ANEXT Cancellation is considered
f100
May 2003 Plato Labs
Analog ApproachAnalog Approach
CLK
DATA
Vin EQUALIZER/CANCELLOR CDR
May 2003 Plato Labs
ClassClass--E 4E 4--Connector Channel Model3Connector Channel Model3
May 2003 Plato Labs
Frequency responses at Slicer Frequency responses at Slicer InputInput
May 2003 Plato Labs
Original PAM5 and Slicer InputOriginal PAM5 and Slicer Input
May 2003 Plato Labs
Slicer Input Eye DiagramSlicer Input Eye Diagram
May 2003 Plato Labs
Retimed CDR PAM5 Data OutputRetimed CDR PAM5 Data Output
May 2003 Plato Labs
FEC FEC
D0 D7 D8 D15 D16 D23 D24 D31
Scrambler
Sc0 Sc7 Sc8 Sc15 Sc16 Sc23 Sc24 Sc31
Coset/Lattice Calculation
Sd0 Sd8 Sd9 Sd17 Sd18 Sd26 Sd27 Sd35
4D 8-state Trellis FEC
A0 B0 C0 D0 A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3
XGMII
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
D3
D2
D1
D0
1.25GBaud/sec (4x312.5MHz)
312.5 MHz
May 2003 Plato Labs
CosetCoset/Lattice Calculation/Lattice Calculation
Sdn(t) = Scn(t) n=0,…, 7Sd8 = Sc7 (t-1) ⊕⊕⊕⊕ Sc6 (t-2) ⊕⊕⊕⊕ Sd8(t-3)
Sdn(t) = Sc(n-1)(t) n=9,…, 16Sd17 = Sc16 (t-1) ⊕⊕⊕⊕ Sc15 (t-2) ⊕⊕⊕⊕ Sd17(t-3)
Sdn(t) = Sc(n-1)(t) n=18,…, 25Sd26 = Sc25 (t-1) ⊕⊕⊕⊕ Sc24 (t-2) ⊕⊕⊕⊕ Sd26(t-3)
Sdn(t) = Sc(n-1)(t) n=27,…, 34Sd35 = Sc34 (t-1) ⊕⊕⊕⊕ Sc33 (t-2) ⊕⊕⊕⊕ Sd35(t-3)
May 2003 Plato Labs
Implementation FeasibilityImplementation Feasibility
• PHY achieves 10Gb/s over 100m Cat6• Single-chip CMOS implementation (0.18µ)• Power/Cost is 2-3X of 1000BASE-T• PAM5 line-signaling• 2Vpp launch voltage• Interface to MAC via XGMII
