10GBASE-T Coding and Modulation: 128-DSQ +...

1 IEEE P802.3an Sep/Oct 2004 Interim

10GBASE10GBASE--T Coding and Modulation:T Coding and Modulation:

128128--DSQ + LDPCDSQ + LDPC

IEEE P802.3an Task ForceOttawa, September 29 – October 1, 2004

revised 27 Sep 04

Gottfried Ungerboeck


Precoding system and definition of SNRPrecoding system and definition of SNR

2wx/E SNR ratio noise-to-Signal σ=

{ }1)-(M3,1, PAM-Man

±±±=∈L

Encoding and symbol

mappingh(D)-1

nkM2 ×

na

( ) 12/2M2xE:MxM n =<≤−

DAC, TX filter, Channel,

RX filter, ADC

FFequalizer

Soft demapping

and decoding

TH precoding

Infobits ny

)D(a )D(w)D(Mk2)D(a)D(y ++=

L2DhDh1)D(h 21 ++=≅

)D(h)D(Mk2)D(a)D(x +=

nx

2wσ

Infobits


22--D constellations for modulation rates in 800+ Mb rangeD constellations for modulation rates in 800+ Mb range

12/)M2( utput Eprecoder oension at dimrgy per Signal ene 2x =

12-PAM

12-P

AM

16-PAM

16-P

AM

24M2 = 32M2 =

20 =∆ 220 =∆

124/48/E 20x ==∆

-0.5115 dB

666.108/)3/256(/E 20x ==∆

{ }1)-(M3,1, PAM-M

±±±=

L

12-PAM2 (with or w/o hole) 128-DSQ (Double SQuare)


128128--DSQ: probability of intraDSQ: probability of intra--subset errors subset errors

14 15 16 17 18 19 20 21 22 23 24 25 26-15

-14

-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

Probability of intra-subset (ISS) error for 9 db set partitioning

(8 subsets)

Probability of intra-subset (ISS) error for 12 db set partitioning

(16 subsets)

⎟⎟⎠

⎞⎜⎜⎝

⎛σ∆

××=∆=∆⎟⎟⎠

⎞⎜⎜⎝

⎛σ∆

××=∆=∆

=∆==−

−−w

44levISS

20

24

w

33levISS

20

23

20

2x

2Q4

21)ePr(:16 ;

2Q4

21)ePr(:8

8;12/)M2(E;16M:DSQ128

[ ]dB/ESNR 2wx σ=

4levISS)ePr( −

3levISS)ePr( −

BER target

BER limited by ISS

distance

This confirms the need for 12 dB set partitioning


Coding, modulation, framing: two variantsCoding, modulation, framing: two variants

Variant I: 128-DSQ + LDPC(1024,821) (M = 384, dH ≥ 14)

• LDPC coding weak w.r.t. to uncoded-bit-only error performance

• Code rate 3.1035 bit/dim

• Framing example: 1 frame = 8 code blocks → modulation rate 821.51 Mbaud, 0.29% overhead for synch and aux. channel.

Variant II: 128-DSQ + LDPC(1024,797) (M = 512, dH ≥ 18)

• Stronger LDPC coding better matched to uncoded-bit-only error performance

• Code rate 3.0566 bit/dim (-0.0469 bit/dim vs. 0.28 dB gain)

• Framing example: 1 frame = 1 code block → modulation rate 833.33 Mbaud (25 MHz x 100/3), 0.28% overhead for synch and aux. channel.


Coding, modulation, framing: variant ICoding, modulation, framing: variant I

128-DSQ modulation with 12 dB set partitioning (16 2-D subsets)and (1024,821) LDPC coding

XGMII2 x (32 TXD + 4 TXC) bits

64+/65trans-codingTX_CLK:

10 GHz / 64 = 156.25 MHz

65-bit blocks

10 GHz / 64 =156.25 MHz

Framing+

Coding+

ModulationModulation rate =

10 GHz/64 x 1024/195 = 820.51 Mbaud

10GBASE-T Frame = 8 code blocks over four pairs = 8 x 1589 bits

= 195 x 65-bit blocks + 37 overhead bits (0.29%)

3*256=768 uncoded info bits

821 coded info bits 203

check bits

Framing example

Code block = 1589 info bits encoded into 512 PAM symbols ( 3.1035 bit/dim )

256 128-DSQ symbols = 512 redundant 16-PAM symbols


Coding, modulation, framing: variant IICoding, modulation, framing: variant II

10GBASE-T Frame =1 Code block over four pairs: 1565 bits =

24 x 65-bit blocks + 5 overhead bits (0.28%)

128-DSQ modulation with 12 dB set partitioning (16 2-D subsets)and (1024,797) LDPC coding

XGMII2 x (32 TXD + 4 TXC) bits

64+/65trans-codingTX_CLK

10 GHz / 64 = 156.25 MHz= 25 MHz x 25/4

65-bit blocks

10 GHz / 64 =156.25 MHz

Framing+

Coding+

ModulationModulation rate

10 GHz/64 x 128/24 = 833.33 Mbaud = 25 MHz x 100/3

3*256=768 uncoded info bits

797 coded info bits 227

check bits

Framing example

Code block = 1565 info bits encoded into 512 PAM symbols ( 3.0566 bit/dim )

256 128-DSQ symbols = 512 redundant 16-PAM symbols

128 PAM symbols


128128--DSQ bit mapping: 3 uncoded bits, 4 coded bits DSQ bit mapping: 3 uncoded bits, 4 coded bits

011 101

001 111

010 100

000 110

0010 0110 1110 1010

0011 0111 1111 1011

0001 0101 1101 1001

0000 0100 1100 1000

4 coded bits:Gray (dH = 1)

3 uncoded bits:pseudo-Gray (dH = 1 or 2)

011 101

001 111

010 100

000 110

011 101

001 111

010 100

000 110

011 101

001 111

010 100

000 110

011 101

001 111

010 100

000 110

011 101

001 111

010 100

000 110

011 101

001 111

010 100

000 110

011 101

001 111

010 100

000 110

011 101

001 111

010 100

000 110

Basic 128-DSQ with cyclic precoding extensions


128128--DSQ bit mappingDSQ bit mapping

0010 0110 1110 1010

0011 0111 1111 1011

0001 0101 1101 1001

0000 0100 1100 1000

c1 c2 c3 c44 coded bits

Gray mapped(dH = 1)

u1 u2 u33 uncoded bits pseudo-Gray

mapped (dH = 1 or 2)

0,0

15,15

0,0

15,15

-15,-15

15,152x

1x

2y

1y

2a

1a

16modxx

1111

yy :

2

1

2

1⎥⎦⎤

⎢⎣⎡

⎥⎦⎤

⎢⎣⎡−

=⎥⎦⎤

⎢⎣⎡

48476R

2 Step

⎥⎦⎤

⎢⎣⎡−⎥⎦

⎤⎢⎣⎡=⎥⎦

⎤⎢⎣⎡

1515

yy2a

a :2

1

2

13 Step

101

011 111 100

001 010 110

000

430221

01

3121

11

322231

21

21323231

31

0i

1i

2i

3ii

ccxccx

cxcx

uuxuux

)u&u()u&u(xu&ux

2,1i,15)xx2x4x8x(0:

⊕=⊕=

==

⊕=⊕=

∨==

=≤+++=≤1 Step


128128--DSQ bit mapping: implementationDSQ bit mapping: implementation

+mod 16 +

3

2

1

uuu

4

3

2

1

cccc

{ }15,3,1a1 ±±±∈ Lx2

x2

+

15−

15−

{ }15,3,1a2 ±±±∈ L+

7-bit label two 16-PAM symbols

2101

111

3121

3131

ccx

cx

uux

u&ux

⊕=

=

⊕=

=

4302

312

3222

213232

ccx

cx

uux

)u&u()u&u(x

⊕=

=

⊕=

∨=

-mod 16 +

2

1

x

x

2

1

y

y


128128--DSQ soft DSQ soft demappingdemapping: 4 coded bits : 4 coded bits

[ ]( ) [ ]( )[ ]( ) [ ]( )∑

∑σ+−−+σ+−−

σ+−−+σ+−−=

k

2222k

2222

2/)3k4(xexp2/)2k4(xexp

2/)1k4(xexp2/)0k4(xexpln)x(llrb

)4mod1x(llrb)x/1cPr()x/0cPr(log)4modx(llrb

)x/1cPr()x/0cPr(log

)4mod1x(llrb)x/1cPr()x/0cPr(log)4modx(llrb

)x/1cPr()x/0cPr(log

224

242

23

23

112

121

11

11

+===

===

+===

===

⎥⎦⎤

⎢⎣⎡=

⎥⎦⎤

⎢⎣⎡

++

⎥⎦⎤

⎢⎣⎡ −

−

2

1

2

1

xx

2/)15s(2/)15s(

5.05.05.05.0

14484476 R

Extended constellation points caused by precoding

2s

1s

15,15

-15,-15

0010 0110 1110 1010

0011 0111 1111 1011

0001 0101 1101 1001

0000 0100 1100 1000

2x

1x

15,15

0,0

c1 c2 c3 c4


The function The function llrb(xllrb(x) )

[ ]( ) [ ]( )[ ]( ) [ ]( ) 4x5.2

5.2x5.0 5.0x0

: 5.3x : x 1.5 : 0.5 x1

2/)3k4(xexp2/)2k4(xexp

2/)1k4(xexp2/)0k4(xexpln)x(llrb 2

k

2222k

2222

≤≤≤≤

≤≤

⎪⎩

⎪⎨⎧

−−

+

σ≅

σ+−−+σ+−−

σ+−−+σ+−−=

∑

∑

1

00 01 11 10 00 01 11 10 01 11 10

0 0.5 1 1.5 2 2.5 3 3.5 4-1.5

-1

-0.5

0

0.5

1

1.5

SNR = 23 dB

x

SNR = 13 dB

SNR = 33 dB

x

x


128128--DSQ + LDPC performance DSQ + LDPC performance

18 19 20 21 22 23 24 25 26-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

128DSQ +LDPC(1024,821)

iter = 6

Hard 128-DSQ symbol-by-

symbol decisions

128-DSQ +LDPC(1024,797)

iter = 6

]dB[SNR

Simulation: precoding extensions included,messages (LLRs) : sssssssxxxx.xxxxx

Problem in implementation of BP algorithm found. Correct result are better by about 0.3 dB.


1212--PAMPAM--T and 128T and 128--DSQ + LDPC performanceDSQ + LDPC performance

20 21 22 23 24 25 26-13

-12

-11

-10

-9

-8

-7

-6

-5

-4

-3

12PAMT +LDPC(1024,821)

iter = 6

Long simulations by Bazhong Shen (Broadcom) without effect of precoding extensions

128DSQ +LDPC(1024,821)

iter = 6

]dB[SNR


Conclusions Conclusions

• 128-DSQ constellation is the natural in-between 8-PAM and 16-PAM modulation

• Bit mapping, precoding, metric calculation, subset decoding: all based on simple logic and power-of-two based arithmetic

• Stronger LDPC(1024,797) code is better matched to uncoded-bit-only error performance

• and leads to simple low-overhead framing and easy clock generation.

10GBASE-T Coding and Modulation: 128-DSQ +...

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