1 An Update on Verilog Ξ – Computer Architecture Lab 28/06/2005 Kypros Constantinides.

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1 An Update on Verilog An Update on Verilog Ξ – Computer Architecture Lab 28/06/2005 Kypros Constantinides

Transcript of 1 An Update on Verilog Ξ – Computer Architecture Lab 28/06/2005 Kypros Constantinides.

Page 1: 1 An Update on Verilog Ξ – Computer Architecture Lab 28/06/2005 Kypros Constantinides.

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An Update on VerilogAn Update on VerilogΞ – Computer Architecture Lab

28/06/2005

Kypros Constantinides

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OutlineOutline The Verilog Hardware Description Language

• Structural Verilog• Behaviorial Verilog

Design Flow• Functional Verification• Logic Synthesis

Supporting Tools Online Resources

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Hardware Description LanguagesHardware Description Languages Need a description one level up from logic gates Work at the level of functional blocks, not logic gates

• Complexity of the functional blocks is up to the designer• A functional unit could be an adder, or even a microprocessor

The description consists of functional blocks and their interconnections

• Describe functional block (not predefined)• Support hierarchical description (function block nesting)

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Verilog HistoryVerilog History Verilog was created in the mid 1980’s. It was designed by taking

features from the most popular HDL language of the time, called HiLo as well as from traditional computer languages such as C

In 1990, Cadence recognized that if Verilog remained a closed language, the pressures of standardization would eventually cause the industry to shift to VHDL. This was the event which "opened" the language

First version was standardized by IEEE 1364 in 1995 Second version in 2001 (still used today) Future Work: Accellera is working on standardizing SystemVerilog 3.1

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High-level view of VerilogHigh-level view of Verilog Verilog descriptions look like programs:

Modules resemble subroutines in that you can write one description and use (instantiate) it in multiple places

Block structure is a key principle• Use hierarchy/modularity to manage complexity

But they aren’t ‘normal’ programs• Module evaluation is concurrent (every block has its own “program counter”)

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Structural VerilogStructural Verilog Structural models

• Are built from gate primitives and/or other modules• They describe the circuit using logic gates — much as you would see in an

implementation of a circuit• Basically you are clearly specifying the structure of the circuit

Identify:• Gate instances, wire names, delay from a or b to f.

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Behavioral ModellingBehavioral Modelling More abstract, no direct description of how a module is

implemented using primitives Mux using behavioral: It looks like C: mix of ifs, case statements, assignments … Different ways for writing descriptions of combinational and

sequential logic

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Behavioral StatementsBehavioral Statements if-then-else

• What you would expect, except that it’s doing 4-valued logic. 1 is interpreted as True; 0, x, and z are interpreted as False

case• What you would expect, except for

4-valued logic• There is no break statement — it is

assumed• Casex statement treats Z/X as

don’t cares

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ASIC Design Traditional FlowASIC Design Traditional Flow Two major steps in the

implementation of the design• Functional Verification: Test the

functional correctness of the high level design (fast)

• Gate Level Simulation: Test the functional correctness of the design post synthesis (slow)

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Functional VerificationFunctional Verification We use simulators to test if the RTL code meets the

functional requirements of the specifications To achieve this we need to write testbench, which generates

clock, reset and required test vectors The testbench is non synthesizable code and drives the

simulation. It’s not part of the design Examples of simulators are VCS and ModelSim

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Logic SynthesisLogic Synthesis Logic Synthesis translates HDL code into a connected set of

standard cells (called a netlist) Technology Library: A collection of optimized standard cells

with known parameters (i.e. NAND2 gate). Provide to synthesis tool timing/area/power constraints

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An ExampleAn Example

HDL CodeSynthesis APR

Testing Prototype

Fabrication

Place & Route

netlist

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Supporting ToolsSupporting Tools Related Supporting Tools:

• Synopsys VCS: RTL verification simulator• Synopsys Design Compiler: Synthesis tool• Synopsys OpenVera (HVL): Based on Verilog, C++, and Java, with

additional constructs specifically for verification• Synopsys Tetramax: Transparent DFT integration. Scan chain &

ATPG• Programming Language Interface (PLI): Lets you add your own

custom applications such as C models, delay calculators, file I/O, and more

• DirectC: It allows Verilog code to call C code directly without any wrapper code

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Online Verilog ResourcesOnline Verilog Resources ASICs the book, Ch. 11:

– http://www.ge.infn.it/~pratolo/verilog/VerilogTutorial.pdf Verilog Quick Reference Guide:

– http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html Alternate Verilog FAQ:

– http://www.angelfire.com/in/verilogfaq/index.html Verilog Introduction

– http://www.see.ed.ac.uk/~gerard/Teach/Verilog/index.html Newsgroup:

– http://groups.google.com/groups?group=comp.lang.verilog Verilog implementation of an Alpha microprocessor at the Register

Transfer Level (IVM)– http://www.crhc.uiuc.edu/ACS/tools/ivm/about.html

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NumbersNumbers Number notation:

• <size> ‘ <base format><number> Examples:

• 4’b1111 // 4 bit binary number• 12’habc //12 bit hexadecimal number• 16’d255 //16 bit decimal number

Z is high impedance, X is don’t care, ? = 0 or 1 or X

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OperatorsOperators Arithmetic

• * multiply• / divide• + add• - subtract• % modulus

Logical• ! Not• && and• || or

Relational• > greater• < less• >= greater-equal• <= less-equal (also used for non-

blocking assignments, later)

Equality• == equal• != not equal• === (case equality)

Bitwise• ~ negation• & and• \ or• ^ xor• ^~ xnor

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Connections: PortsConnections: Ports Keywords:

• input - input• output - output• inout - bi-directional

Ports do not store information Examplemodule ex (a, b, c, out)

output out;

input a, b, c;

endmodule

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WiresWires Wires

• Connection between hardware elements (visualize as a node in the circuit)• Module connections• Used to connect signals from sensitivity list• Memoryless - Must be continuously driven by an assignment statement (assign)• Assigned outside of always blocks

Example:wire a; // declared wire net

wire b = 1’b0 // tied to zero at declaration

(alternatively: wire b; assign b = 1’b0;

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Memory ElementsMemory Elements Register

• Keyword = reg• Represents storage in that its value is whatever was most recently

(procedurally) assigned to it - But it does NOT necessarily instantiate an actual register• Assigned within always blocks

Examples:reg clock; // clock

reg [0:4] vec_reg // 5 bit register vector

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Blocking Vs Non-BlockingBlocking Vs Non-Blocking Relates to scheduling of events Blocking

• Ex:begin A = B; B = A;end

• Each assignment is completed before moving to the next line • In this case, value held in B is assigned to A, and then the value assigned in A (same as in B) is then

assigned back to B. Non-blocking (preferable in sequential elements)

• Ex:begin A <= B; B <= A;end

• Values on RHS of both expressions are held in temp locations, all assignments are done concurrently à A and B are swapped

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Full-Adder CodeFull-Adder Code Sample Code

module full_adder (a, b, ci, sum, co);

input/output signal list

input a, b, ci; //input declaration

output sum, co; //output declaration

assign sum = a ^ b ^ ci;

assign co = (a & b) | (a & ci) | (b & ci);

endmodule

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Positive Edge-Triggered registers with resetPositive Edge-Triggered registers with resetmodule ff1(d,clk,reset,q)

input d, clk, reset;output q;reg q;

always @(posedge clk) if (reset == 1) q <= 0; else q <= d;

ORalways @(posedge clk or posedge reset) if (reset == 1) q <= 0; else q <= d;

endmodule