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Transcript of خ© RF Digital Attenuator Product Description 5-bit, 31 dB, 9 ... 24 23 22 21 20 19 7 8 9 101112...

  • Page 1 of 11

    Document No. 70-0252-05 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.

    The PE43503 is a HaRP™-enhanced, high linearity, 5-bit RF Digital Step Attenuator (DSA) covering a 31 dB attenuation range in 1 dB steps. The Peregrine 50Ω RF DSA provides a serial CMOS control interface. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with Vdd due to on-board regulator. This next generation Peregrine DSA is available in a 4x4 mm 24-lead QFN footprint. The PE43503 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS.

    Product Specification

    50 Ω RF Digital Attenuator 5-bit, 31 dB, 9 kHz - 6.0 GHz Product Description

    Figure 2. Functional Schematic Diagram

    PE43503

    Features  HaRP™-enhanced UltraCMOS™ device

     Attenuation: 1 dB steps to 31 dB

     High Linearity: Typical +58 dBm IP3  Excellent low-frequency performance

     3.3 V or 5.0 V Power Supply Voltage

     Fast switch settling time

     Programming Modes:  Direct Parallel  Latched Parallel  Serial

     High-attenuation state @ power-up (PUP)

     CMOS Compatible

     No DC blocking capacitors required

     Packaged in a 24-lead 4x4x0.85 mm QFN

    Figure 1. Package Type

    Control Logic Interface

    RF Input RF Output

    Switched Attenuator Array

    Serial In

    LE

    CLK

    A0 A1 A2

    Parallel Control 5

    P/S

    24-lead 4x4x0.85 mm QFN Package

    OB SO

    LE TE

    RE PL

    AC E

    W ITH

    P E4

    37 11

    Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

  • Product Specification PE43503

    Page 2 of 11

    ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0252-05 │ UltraCMOS™ RFIC Solutions

    -1

    0

    1

    2

    0 4 8 12 16 20 24 28 32

    Attenuation Setting (dB)

    S te

    p E

    rr or

    (d B

    )

    200MHz 900MHz 1800MHz 2200MHz 3000MHz 4000MHz 5000MHz 6000MHz

    -2

    -1.5

    -1

    -0.5

    0

    0.5

    1

    1.5

    2

    0 4 8 12 16 20 24 28 32

    Attenuation Setting (dB)

    At te

    nu at

    io n

    Er ro

    r (d

    B)

    200MHz 900MHz 1800MHz 2200MHz 3000MHz 4000MHz 5000MHz 6000MHz

    -2

    -1.5

    -1

    -0.5

    0

    0.5

    1

    1.5

    2

    0 1000 2000 3000 4000 5000 6000

    Frequency (GHz)

    Bi t E

    rr or

    (d B)

    1dB State 2dB State 4dB State 8dB State 16dB State 31dB State

    900 MHz 2200 MHz 3800 MHz 5800 MHz

    5 10 15 20 25 300 35

    5

    10

    15

    20

    25

    30

    0

    35

    Attenuation State

    A tte

    nu at

    io n

    d B

    Attenuation

    Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V

    Performance Plots

    Parameter Test Conditions Frequency Min. Typical Max. Units Frequency Range 9 kHz 6 GHz Attenuation Range 1 dB Step 0 – 31 dB

    Insertion Loss 9 kHz ≤ 6 GHz 2.4 2.9 dB

    Attenuation Error

    0dB - 31dB Attenuation settings 0dB - 21dB Attenuation settings 22dB - 31dB Attenuation settings 0dB - 31dB Attenuation settings

    9 kHz ≤ 4 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz 4 GHz ≤ 6 GHz

    ±(0.3+3%) +0.4+9% +2.4+0% -0.2-3%

    dB dB dB dB

    Relative Phase All States 9 kHz ≤ 6 GHz 72 ° P1dB (note 1) Input 20 MHz - 6 GHz 30 32 dBm Input IP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz – 6 GHz +58 dBm Return Loss DC ≤ 6 GHz 17 dB

    Switching Speed 50% DC CTRL to 10% / 90% RF 650 ns

    Typical Spurious Value 1 MHz -115 dBm

    Video Feed Through 10 mVpp

    Settling Time RF settled to within 0.05 dB of final value RBW = 5 MHz, Averaging ON. 4 µs

    RF Trise/Tfall 10% / 90% RF 400 ns

    *Monotonicity is held so long as Step-Error does not cross below -1

    Figure 3. 1dB Step Error vs. Frequency * Figure 4. 1dB Attenuation vs. Attenuation State

    Figure 5. 1dB Major State Bit Error Figure 6. 1dB Attenuation Error vs. Frequency

    (d B

    ) Note 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 3.

    OB SO

    LE TE

    RE PL

    AC E

    W ITH

    P E4

    37 11

    Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

  • Product Specification PE43503

    Page 3 of 11

    Document No. 70-0252-05 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.

    30

    35

    40

    45

    50

    55

    60

    65

    70

    0 500 1000 1500 2000 2500 3000 3500 4000 4500

    Frequency (MHz)

    In pu

    t I P3

    (d Bm

    )

    0dB 1dB 2dB 4dB 8dB 16dB 31dB

    -2

    -1.5

    -1

    -0.5

    0

    0.5

    1

    1.5

    2

    0 4 8 12 16 20 24 28 32

    Attenuation Setting (dB)

    At te

    nu at

    io n

    Er ro

    r ( dB

    )

    -40C +25C +85C

    0

    20

    40

    60

    80

    100

    120

    140

    0 1 2 3 4 5 6 7 8

    Frequency (GHz)

    Re la

    tiv e

    Ph as

    e Er

    ro r (

    De g) 0dB 1dB 2dB 4dB 8dB 16dB 31dB

    -45

    -40

    -35

    -30

    -25

    -20

    -15

    -10

    -5

    0

    0 1 2 3 4 5 6 7 8 9

    Frequency (GHz)

    Re tu

    rn L

    os s

    (d B)

    0dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31dB

    -40

    -35

    -30

    -25

    -20

    -15

    -10

    -5

    0

    0 1 2 3 4 5 6 7 8 9

    Frequency (GHz)

    In pu

    t R et

    ur n

    Lo ss

    (d B)

    0dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31dB

    -3.5

    -3

    -2.5

    -2

    -1.5

    -1

    -0.5

    0

    0 2 4 6 8 10

    Frequency (GHz)

    In se

    rti on

    L os

    s (d

    B)

    -40C +25C +85C

    Figure 7. Insertion Loss vs. Temperature Figure 8. Input Return Loss vs. Attenuation @ T = +25C

    Figure 9. Output Return Loss vs. Attenuation @ T = +25C

    Figure 10. Relative Phase vs. Frequency

    Figure 11. Attenuation Error vs. Temperature @ 6 GHz

    Figure 12. Input IP3 vs. Frequency

    OB SO

    LE TE

    RE PL

    AC E

    W ITH

    P E4

    37 11

    Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

  • Product Specification PE43503

    Page 4 of 11

    ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0252-05 │ UltraCMOS™ RFIC Solutions

    0

    5

    10

    15

    20

    25

    30

    1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09

    Hz

    P in

    (d Bm

    )

    1

    2

    3

    4

    5

    6

    18

    17

    16

    15

    14

    13

    24 23 22 21 20 19

    7 8 9 10 11 12

    GND C1 C2 C4 C8 C16

    NC

    VDD

    P/S

    GND

    RF1

    GND

    SI

    CLK

    LE

    GND

    RF2

    GND

    G N

    D

    G N

    D

    G N

    D

    G N

    D

    G N

    D

    G N

    D Exposed

    Solder Pad

    Table 2. Pin Descriptions

    Figure 13. Pin Configuration (Top View)

    Pin No. Pin Name Description 1 NC No Connect

    2 VDD Power supply pin

    3 P/S Serial/Parallel mode select 4 GND Ground

    5 RF1 RF1 port

    6 GND Ground

    7 - 12 GND Ground

    13 GND Ground

    14 RF2 RF2 port

    15 GND Ground

    16 LE Serial interface Latch Enable input

    17 CLK Serial interface Clock input

    18 SI Serial interface Data input

    19 C16 (D6) Parallel control bit, 16 dB

    20 C8 (D5) Parallel control bit, 8 dB

    21 C4 (D4) Parallel control bit, 4 dB

    22 C2 (D3) Parallel control bit, 2 dB

    23 C1 (D2) Parallel control bit, 1 dB 24 GND Ground

    Note: Ground C1, C2, C4, C8, C16 if not in use.

    Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD- sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating.

    Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation.

    Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up.

    Switching Frequency The PE435