ΛΟΓΙΚΗ ΣΧΕΔΙΑΣΗ

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ΤΕΧΝΟΛΟΓΙΚΟ ΕΚΠΑΙΔΕΥΤΙΚΟ ΙΔΡΥΜΑ (Τ.Ε.Ι.) ΣΤΕΡΕΑΣ ΕΛΛΑΔΑΣ ΣΧΟΛΗ ΤΕΧΝΟΛΟΓΙΚΩΝ ΕΦΑΡΜΟΓΩΝ ΤΜΗΜΑ ΗΛΕΚΤΡΟΝΙΚΩΝ ΜΗΧΑΝΙΚΩΝ Τ.Ε. ΛΟΓΙΚΗ ΣΧΕΔΙΑΣΗ Δρ. ΑΣΗΜΑΚΗΣ ΝΙΚΟΛΑΟΣ ΚΑΘΗΓΗΤΗΣ ΛΑΜΙΑ 2014
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ΤΕΧΝΟΛΟΓΙΚΟ ΕΚΠΑΙΔΕΥΤΙΚΟ ΙΔΡΥΜΑ (Τ.Ε.Ι.) ΣΤΕΡΕΑΣ ΕΛΛΑΔΑΣ ΣΧΟΛΗ ΤΕΧΝΟΛΟΓΙΚΩΝ ΕΦΑΡΜΟΓΩΝ ΤΜΗΜΑ ΗΛΕΚΤΡΟΝΙΚΩΝ ΜΗΧΑΝΙΚΩΝ Τ.Ε. ΛΟΓΙΚΗ ΣΧΕΔΙΑΣΗ Δρ. ΑΣΗΜΑΚΗΣ ΝΙΚΟΛΑΟΣ ΚΑΘΗΓΗΤΗΣ ΛΑΜΙΑ 20 14. ΛΟΓΙΚΗ ΣΧΕΔΙΑΣΗ. ΑΡΙΘΜΗΤΙΚΑ ΣΥΣΤΗΜΑΤΑ ΚΩΔΙΚΕΣ ΛΟΓΙΚΕΣ ΠΥΛΕΣ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ - PowerPoint PPT Presentation

Transcript of ΛΟΓΙΚΗ ΣΧΕΔΙΑΣΗ

  • (...) ..

    .

    2014

  • . * FLIP-FLOP

  • . *

  • . * (radix) r n+m+1 0 r-1, :(A)r=an an-1a1 a0 . a-1 a-2a-m

    ( 10) :(A)10=anrn+ an-1rn-1++ a1r1+ a0r0+ a-1r-1+a-2r-2++ a-mr-m

  • . * 2, 8, 10, 16

    10

    2

    8

    16

    00

    0000

    00

    0

    01

    0001

    01

    1

    02

    0010

    02

    2

    03

    0011

    03

    3

    04

    0100

    04

    4

    05

    0101

    05

    5

    06

    0110

    06

    6

    07

    0111

    07

    7

    08

    1000

    10

    8

    09

    1001

    11

    9

    10

    1010

    12

    A

    11

    1011

    13

    B

    12

    1100

    14

    C

    13

    1101

    15

    D

    14

    1110

    16

    E

    15

    1111

    17

    F

  • . * (1110.011)2 = 1x23 + 1x22 + 1x21 + 0x20 + 0x2-1 + 1x2-2 + 1x2-3 = (14.375)10 (B65F)16 = 11x163 + 6x162 + 5x161 + 15x160 = (46687)10

  • . *

    (41.8125)10 = (101001.1101)2 0.8125x2=1+0.62500.6250x2=1+0.25000.2500x2=0+0.50000.5000x2=1+0.0000

    (225)10 = (E1)16

    41

    2

    1

    20

    2

    0

    10

    2

    0

    5

    2

    1

    2

    2

    0

    1

    2

    1

    0

    225

    16

    1

    14

    16

    E=14

    0

  • . *

  • . * n bit 2n . :- bits ( BCD 8 4 2 1) - ( Gray)

  • . * BCD, EXCESS-3, 8 4 2 -1, GRAY

    BCD

    8 4 2 1

    excess-3

    (BCD+3)

    8 4 -2 -1

    Gray

    0

    0000

    0011

    0000

    0000

    1

    0001

    0100

    0111

    0001

    2

    0010

    0101

    0110

    0011

    3

    0011

    0110

    0101

    0010

    4

    0100

    0111

    0100

    0110

    5

    0101

    1000

    1011

    0111

    6

    0110

    1001

    1010

    0101

    7

    0111

    1010

    1001

    0100

    8

    1000

    1011

    1000

    1100

    9

    1001

    1100

    1111

    1101

  • . * ASCII (American Standard Code for Interghange Information) 7 bit 128 . ASCII 94 34 (control characters), 128 . :- 26 A-Z- 26 a-z- 10 0-9- 32

  • . * ASCII

    000

    001

    010

    011

    100

    101

    110

    111

    0000

    NUL

    DLE

    SP

    0

    @

    P

    `

    p

    0001

    SOH

    DC1

    !

    1

    A

    Q

    a

    q

    0010

    STX

    DC2

    "

    2

    B

    R

    b

    r

    0011

    ETX

    DC3

    #

    3

    C

    S

    c

    s

    0100

    EOT

    DC4

    $

    4

    D

    T

    d

    t

    0101

    ENQ

    NAK

    %

    5

    E

    U

    e

    u

    0110

    ACK

    SYN

    &

    6

    F

    V

    f

    v

    0111

    BEL

    ETB

    '

    7

    G

    W

    g

    w

    1000

    BS

    CAN

    (

    8

    H

    X

    h

    x

    1001

    HT

    EM

    )

    9

    I

    Y

    i

    y

    1010

    LF

    SUB

    *

    :

    J

    Z

    j

    z

    1011

    VT

    ESC

    +

    ;

    K

    [

    k

    {

    1100

    FF

    FS

    '

    N

    ^

    n

    ~

    1111

    SI

    US

    /

    ?

    O

    -

    o

    DEL

  • . * (error detection code) , bit "0" "1" "1" "0".

  • . * BIQUINARY biquinary 7 bit 5 0 4 3 2 1 0. "1" "0".

    biquinary

    5043210

    0

    0100001

    1

    0100010

    2

    0100100

    3

    0101000

    4

    0110000

    5

    1000001

    6

    1000010

    7

    1000100

    8

    1001000

    9

    1010000

  • . * BIQUINARY biquinary : , "1" . "1", . :1000001010010052 , "1".

  • . * BIQUINARY :100000101001015? "1". , 0100100 ( 2) 0100001 ( 0), 52 50.

  • . *BIT (PARITY BIT) bit (Parity Bit).

    (M2M1M0) bit (P), (M2M1M0P) "1" ( ) "1" ( ).

  • . *

    Parity Bit

    000

    1

    0

    001

    0

    1

    010

    0

    1

    011

    1

    0

    100

    0

    1

    101

    1

    0

    110

    1

    0

    111

    0

    1

  • . * BIT ( ) . :100 0001 0101 1011 14153 , Parity Bit .

  • . * BIT :101 1010 1110 1011 15263 Parity Bit. . . .

  • . * (error detection and error correction code) , .

  • . * bit (Parity Bit): PB1 PB2 . :

    , Parity Bit .

    PB1

    9

    1

    0

    0

    1

    0

    2

    0

    0

    1

    0

    1

    12

    1

    1

    0

    0

    0

    1

    0

    0

    0

    1

    1

    PB2

    0

    1

    1

    0

    0

  • . * ( ). :

    ( ), 0010 0000 ( ).

    PB1

    9

    1

    0

    0

    1

    0

    0

    0

    0

    0

    0

    1

    12

    1

    1

    0

    0

    0

    1

    0

    0

    0

    1

    1

    PB2

    0

    1

    1

    0

    0

  • . * HAMMING Hamming k bit (Parity Bit) n bit , 2k-1-kn. o Hamming ( ). k bit . , n+k bit. k bit 2 (1, 2, 4, 8,...). bit ( bit ), .

  • . * BIT HAMMING 11000100 (n=8) bit (k=4):P1=XOR(3,5,7,9,11)=XOR(11000)=0P2=XOR(3,6,7,10,11)=XOR(10010)=0P4=XOR(5,6,7,12)=XOR(1000)=1P8=XOR(9,10,11,12)=XOR(0100)=1 n+k=12 bit001110010100 bit 1, 2, 4, 8. XOR , bit "1" XOR "1" bit "0" XOR "1".

  • . * HAMMING k=4 bit , :C1=XOR(1,3,5,7,9,11)=XOR(011000)=0C2=XOR(2,3,6,7,10,11)=XOR(010010)=0C4=XOR(4,5,6,7,12)=XOR(11000)=0C8=XOR(8,9,10,11,12)=XOR(10100)=0 bit C=C8 C4 C2 C1 C=0 , 11000100 .

  • . * HAMMING n+k=12 bit 100001111010 k=4 bit :C1=XOR(1,3,5,7,9,11)=XOR(100111)=0C2=XOR(2,3,6,7,10,11)=XOR(001101)=1C4=XOR(4,5,6,7,12)=XOR(00110)=0C8=XOR(8,9,10,11,12)=XOR(11010)=1 bit C=C8 C4 C2 C1 C0 C=1010 ( 10). 100001111010 100001111110 "0" "1" 10 00111010 00111110

  • . * BOOLE NOT, AND OR NAND NOR XOR XNOR

  • . * BOOLE Boole ={0,1} + (OR) (AND) :

    x

    y

    x+y

    x(y

    0

    0

    0

    0

    0

    1

    1

    0

    1

    0

    1

    0

    1

    1

    1

    1

  • . * BOOLE ( Huntington)

    1. . + (OR). (AND)2. . x+0=0+x=x . x1=1x=x3. . x+y=y+x . xy=yx4. . x(y+z)=xy+xz . x+(yz)=(x+y)(x+z)5. (NOT) . x+x'=1 . xx'=0

  • . * BOOLE

    1. . x+x=x. xx=x2. . x+1=1. x0=03. (x')'=x4. . x+y+z=x+(y+z)=(x+y)+z. xyz=x(yz)=(xy)z5. . x+xy=x. x(x+y)=x6. De Morgan . (x+y)'=x'.y. (x.y)'=x'+y'

  • . * NOT, AND OR Boole NOT, AND OR. . . NOT, AND OR. , ( ) . .

  • . * , 1 0. 1 - igh Level (.. 5V), , 0 - Low Level (.. 0V) L. 1 3.5V - 5V, 0 0V 1.5V.

  • . * NOT, AND OR NOT, AND OR :

  • . * NOT, AND OR 1 1. H AND 1 1. OR 1 1.

    NOT

    AND

    OR

    x

    x

    x

    y

    x(y

    x

    y

    x+y

    0

    1

    0

    0

    0

    0

    0

    0

    1

    0

    0

    1

    0

    0

    1

    1

    1

    0

    0

    1

    0

    1

    1

    1

    1

    1

    1

    1

  • . * NAND NOR NAND NOR :

  • . * NAND NOR NAND AND NOT. NAND 1" 0. NOR OR NOT. NOR 1 0.

    NAND

    NOR

    x

    y

    (xy)

    x

    y

    (x+y)

    0

    0

    1

    0

    0

    1

    0

    1

    1

    0

    1

    0

    1

    0

    1

    1

    0

    0

    1

    1

    0

    1

    1

    0

  • . * AND OR AND OR . AND OR , :x+y+z=x+(y+z)=(x+y)+zxyz=x(yz)=(xy)z

  • . * AND (3)

    A

    B

    C

    ABC

    0

    0

    0

    0

    0

    0

    1

    0

    0

    1

    0

    0

    0

    1

    1

    0

    1

    0

    0

    0

    1

    0

    1

    0

    1

    1

    0

    0

    1

    1

    1

    1

  • . * NAND NOR NAND NOR .

    NAND NOR NOT AND OR .

  • . * NOR (4)

    A

    B

    C

    D

    (A+B+C+D)

    0

    0

    0

    0

    1

    0

    0

    0

    1

    0

    0

    0

    1

    0

    0

    0

    0

    1

    1

    0

    0

    1

    0

    0

    0

    0

    1

    0

    1

    0

    0

    1

    1

    0

    0

    0

    1

    1

    1

    0

    1

    0

    0

    0

    0

    1

    0

    0

    1

    0

    1

    0

    1

    0

    0

    1

    0

    1

    1

    0

    1

    1

    0

    0

    0

    1

    1

    0

    1

    0

    1

    1

    1

    0

    0

    1

    1

    1

    1

    0

  • . * XOR XNOR XOR XNOR :

  • . * XOR XNOR XOR "1" . XNOR "1" .

    XOR

    XNOR

    x

    y

    x(y

    x

    y

    x(y

    0

    0

    0

    0

    0

    1

    0

    1

    1

    0

    1

    0

    1

    0

    1

    1

    0

    0

    1

    1

    0

    1

    1

    1

  • . * XOR XNOR XOR XNOR :xy=xy+xyxy=xy+xy XOR XNOR :xy=(xy)

  • . * - CHIP 7400 74

  • . * - CHIP (integrated circuits) . (chip) . chip . chip (pin) .

  • . * (Scale Integration), :

    (Scale Integration)

    SSI (Small Scale Integration)

    < 12

    MSI (Medium Scale Integration)

    12 100

    LSI (Large Scale Integration)

    100 1000

    VLSI (Very Large Scale Integration)

    1000 100000

    ULSI (Ultra Large Scale Integration)

    > 100000

  • . * BIPOLARCMOS (Complementary Metal-Oxide Semiconductor)BICMOS (Bipolar CMOS)ECL (Emitter Coupled Logic)

  • . * - Fun Out ( )- Power Dissipation ( )- Propagation Delay ( )- Noise Margin ( )

  • . *

    SN (Texas Instruments)

    DM (Fairchild Semiconductor)

    74 (0o C ( 70o C )

    64 (-40o C ( 85o C )

    54 (-55o C ( 125o C )

    S (Schottky)

    LS (Low-power Schottky)

    ALS (Advanced Low-power Schottky)

    C (CMOS)

    HC (High-speed CMOS TTL)

    HTC (High-speed CMOS TTL compatible)

    00 4 NAND 2

    04 6 NOT

    08 4 AND 2

    32 4 OR 2

    D/DW (SOIC Small Outline Integrated Circuit)

    DB/DL (SSOP)

    DGG (TSSOP)

    FK (LCCC)

    N/P (PDIP Plastic Dual In Package)

    NS (SOP)

  • . * 7400 chip standard 74 TTL 74 . chip 7400 NAND TTL.

    Vcc

    4B

    4A

    4Y

    3B

    3A

    3Y

    14

    13

    12

    11

    10

    9

    8

    7400

    1

    2

    3

    4

    5

    6

    7

    1A

    1B

    1Y

    2A

    2B

    2Y

    GND

  • . * 7400 chip Vcc ( - 1) 2.4V-5V 3.5V GND ( - 0) 0V-0.4V 0.2V.

    pin

    1

    1A

    1

    2

    1B

    1

    3

    1Y

    1

    4

    2A

    2

    5

    2B

    2

    6

    2Y

    2

    7

    GND

    ( 0)

    8

    3Y

    3

    9

    3A

    3

    10

    3B

    3

    11

    4Y

    4

    12

    4A

    4

    13

    4B

    4

    14

    Vcc

    ( 1)

  • . * (Data Sheets) : (General Description) (Connection Diagram) (Function Table) (Absolute Maximum Ratings) (Recommended Operation Conditions) (Electrical Characteristics) (Switching Characteristics). (Physical Dimensions)

  • . * 74

    chip

    7400

    4 NAND 2

    7402

    4 NOR 2

    7404

    6 NOT

    7408

    4 AND 2

    7410

    3 NAND 3

    7411

    3 AND 3

    7420

    2 NAND 4

    7421

    2 AND 4

    7427

    7430

    1 NAND 8

    7432

    4 OR 2

    7486

    4 XOR 2

  • . *

    KARNAUGH ME KARNAUGH

  • . * n Boole n , Boole . (AND) ( , xy=xy).

    : (), NOT, AND, OR.

  • . * n , 1 0., 2n. , : 1 0. -.

  • . * Y A, B C : 8 (=23) 3 . Y=1 A=0 (AND) B=0 (AND) C=1 (OR)A=1 (AND) B=1 (AND) C=0, Y :Y=ABC+ABC

    A

    B

    C

    Y

    0

    0

    0

    0

    0

    0

    1

    1

    0

    1

    0

    0

    0

    1

    1

    0

    1

    0

    0

    0

    1

    0

    1

    0

    1

    1

    0

    1

    1

    1

    1

    0

  • . * , () ( 1) ( 0). , () ( 0) ( 1). n 2n 2n .

  • . * : ( ) ( ) .

  • . * Y=Y(x,y,z) x, y z x (Most Significant Bit - MSB) z (Least Significant Bit - LSB) (23=8). :

    : Y=x'y'z+xy'z'+xyz=(1,4,7) : Y=(x+y+z) (x+y'+z) (x+y'+z') (x'+y+z') (x'+y'+z)=(0,2,3,5,6)

    x

    y

    z

    Y

    0

    0

    0

    0

    m0=x'y'z'

    M0=x+y+z

    0

    0

    1

    1

    m1=x'y'z

    M1=x+y+z'

    0

    1

    0

    0

    m2=x'yz'

    M2=x+y'+z

    0

    1

    1

    0

    m3=x'yz

    M3=x+y'+z'

    1

    0

    0

    1

    m4=xy'z'

    M4=x'+y+z

    1

    0

    1

    0

    m5=xy'z

    M5=x'+y+z'

    1

    1

    0

    0

    m6=xyz'

    M6=x'+y'+z

    1

    1

    1

    1

    m7=xyz

    M7=x'+y'+z'

  • . * KARNAUGH Karnaugh . Karrnaugh , Karnaugh .

  • . * KARNAUGH2

    B

    0

    1

    0

    0

    1

    A

    1

    2

    3

  • . * KARNAUGH3

    B

    00

    01

    11

    10

    0

    0

    1

    3

    2

    A

    1

    4

    5

    7

    6

    C

  • . * KARNAUGH4

    C

    00

    01

    11

    10

    00

    0

    1

    3

    2

    01

    4

    5

    7

    6

    B

    A

    11

    12

    13

    15

    14

    10

    8

    9

    11

    10

    D

  • . * KARNAUGH Karnaugh 1 Karnaugh 1 0 ( ) Karnaugh 0. , . . Karnaugh X.

  • . * KARNAUGH Y=ABC+ABC+ABC Karnaugh:

    B

    00

    01

    11

    10

    0

    1

    A

    1

    1

    1

    C

  • . *H KARNAUGH Karnaugh, : . Karnaugh 1 . 1 2, 4, 8, 16 ( , , ). . 1 . ( ).

  • . *H Karnaugh X 0 1, , . X 1 .

  • . * Y=A(BC+BCD)+ABCD , : Y=ABC+ABCD+ABCD=ABCD+ABCD+ABCD+ABCD=(10,11,14,15) 14 15 Karnaugh. ( D) 10 11 Karnaugh.=C

    C

    00

    01

    11

    10

    00

    01

    B

    A

    11

    1

    1

    10

    1

    1

    D

  • . * Y=ABCD+ABD+ABCD ABCD BCD

    Y=AB+ACD

    C

    00

    01

    11

    10

    00

    1

    X

    01

    X

    B

    A

    11

    X

    1

    1

    1

    10

    D

  • . *

  • . * () n m m n . n , 1 0. , 2n. , : 1 0. -.

  • . * : Karnaugh

    .

  • . * () 3-bit 3, NOT AND OR . A, B C, 0 7 ( 3 bit 23=8 ) Y. 1 3-bit 3.

  • . * :

    A

    B

    C

    Y

    0

    0

    0

    0

    1

    1

    0

    0

    1

    1

    2

    0

    1

    0

    1

    3

    0

    1

    1

    0

    4

    1

    0

    0

    0

    5

    1

    0

    1

    0

    6

    1

    1

    0

    0

    7

    1

    1

    1

    0

  • . * Y=1 A=0 (AND) B=0 (AND) C=0 (OR)A=0 (AND) B=0 (AND) C=1 (OR)A=0 (AND) B=1 (AND) C=0, :Y=ABC+ABC+ABC

  • . * :Y=AB+AC Karnaugh :

    B

    00

    01

    11

    10

    0

    1

    1

    1

    A

    1

    C

  • . * :Y=AB+AC=A(B+C)=A(BC)=(A+BC) , , . , . , .

  • . * 1. NOT Y=(A+BC) , . 2. OR A+BC, . 3. AND , BC, .

  • . *

  • . * NAND NOR (universal gates) NAND NOR .

  • . * NAND NOT AND OR NAND . NOT, AND OR, ND .

  • . * NOR NOT AND OR NOR . NOT, AND OR, NOR .

  • . * NAND/NOR 2 NAND NOR , NOT, AND OR . NAND NOR , .

  • . * NAND 2 NAND : Z=AB+C NOT, AND OR:

  • . * NAND :

  • . * NAND . :

  • . * NOR 2 NOR :Z=AB+C De Morgan :Z=AB+C=((AB)C)=((A+B)C)=(A+B)+C=(((A+B)+C))H NOR :

  • . * NAND NOR (universal gates) NAND NOR .

  • . * NAND/NOR - , NAND , NOR- NAND , NAND NOR , NOR- - , ( )

  • . * -

  • . * . x y ( bit ) C (-carry) S (-sum). S=xy+xy=xyC=xy

    x

    y

    C

    S

    0

    0

    0

    0

    0

    1

    0

    1

    1

    0

    0

    1

    1

    1

    1

    0

  • . * . x, y ( bit ) z ( ) C ( -carry) S (-sum).S=(xy)zC=xy+(xy)z

    x

    y

    z

    C

    S

    0

    0

    0

    0

    0

    0

    0

    1

    0

    1

    0

    1

    0

    0

    1

    0

    1

    1

    1

    0

    1

    0

    0

    0

    1

    1

    0

    1

    1

    0

    1

    1

    0

    1

    0

    1

    1

    1

    1

    1

  • . * . x y ( bit ) B () D (). D=xyB=xy

    x

    y

    B

    D

    0

    0

    0

    0

    0

    1

    1

    1

    1

    0

    0

    1

    1

    1

    0

    0

  • . * . x, y ( bit ) z ( ) B ( ) D (). D=(xy)zB=xy+(xy)z

    x

    y

    z

    B

    D

    0

    0

    0

    0

    0

    0

    0

    1

    1

    1

    0

    1

    0

    1

    1

    0

    1

    1

    1

    0

    1

    0

    0

    0

    1

    1

    0

    1

    0

    0

    1

    1

    0

    0

    0

    1

    1

    1

    1

    1

  • . * 4-bit (chip 7483) C0 (pin 13) 4-bit A=A4A3A2A1 (pin 1, 3, 8, 10) B=B4B3B2B1 (pin 16, 4, 7, 11) 5-bit =C44321 (pin 14, 15, 2, 6, 9), C4 (pin 14) . A+B+C0. C0=0 =A+B C0=1 =A+B+1 15 C4=1, 15 C4=0.

  • . * 7483

  • . * - / 4-bit bit C0 (switch C0) 4-bit a=a4a3a2a1 (switches a4, a3, a2, a1) b=b4b3b2b1 (switches b4, b3, b2, b1) C4 (led C4) 4-bit 4321 (led 4, 3, 2, 1). a4a3a2a1 / A4A3A2A1 . b4b3b2b1 / B4B3B2B1 XOR2, bit C0, .

  • . * C0=0 / a+b. 5-bit =C44321. 15 C4=1, 15 C4=0. C0=1 / . ab a-b, C4=1 4-bit 4321 a-b. a
  • . *

    7486

    7483

    pin

    connection

    pin

    connection

    1

    switch C0

    1

    switch a4

    2

    switch b1

    2

    led 3

    3

    pin 11 7483

    3

    switch a3

    4

    switch C0

    4

    pin 8 7486

    5

    switch b2

    5

    Vcc

    6

    pin 7 7483

    6

    led 2

    7

    GND

    7

    pin 6 7486

    8

    pin 4 7483

    8

    switch a2

    9

    switch C0

    9

    led 1

    10

    switch b3

    10

    switch a1

    11

    pin 16 7483

    11

    pin 3 7486

    12

    switch C0

    12

    GND

    13

    switch b4

    13

    switch C0

    14

    Vcc

    14

    led C4

    15

    led 4

    16

    pin 11 7486

  • . * C0=0 C4=0 /:C0=0, a4a3a2a1=0011 b4b3b2b1=0100 : C0=0, A4A3A2A1=0011 B4B3B2B1=0100 : C4=0 4321=0111 0011+0100=00111

  • . * C0=0 C4=1 /:C0=0, a4a3a2a1=1100 b4b3b2b1=1001 :C0=0, A4A3A2A1=1100 B4B3B2B1=1001 : C4=1 4321=0101 1100+1001=10101

  • . * C0=1 C4=1 /:C0=1, a4a3a2a1=1100 b4b3b2b1=1001 :C0=1, A4A3A2A1=1100 B4B3B2B1=0110 : C4=1 4321=0011 1100-1001=0011

  • . * C0=1 C4=0 /:C0=1, a4a3a2a1=1001 b4b3b2b1=1100 :C0=1, A4A3A2A1=1001 B4B3B2B1=0011 : C4=0 4321=1101 2 1100-1001=0011-1 0011 = 1100-2 0011 = -1 0011 + 1 = 1100 + 1=1101

  • . *

  • . * (Encoder) 2nxn 2n n ..

    .

  • . * 4X2 4x2 D0, D1, D2 D3 x y. x=D2+D3y=D1+D3

    D0

    D1

    D2

    D3

    x

    y

    1

    0

    0

    0

    0

    0

    0

    1

    0

    0

    0

    1

    0

    0

    1

    0

    1

    0

    0

    0

    0

    1

    1

    1

  • . * 1, . .

  • . * 4x2 4x2 D3 ( ) D0 ( ) D0, D1, D2 D3 x, y z ( ). x=D2+D3y=D1D2+D3z=D0+D1+D2+D3

    D0

    D1

    D2

    D3

    x

    y

    z

    0

    0

    0

    0

    X

    X

    0

    1

    0

    0

    0

    0

    0

    1

    X

    1

    0

    0

    0

    1

    1

    X

    X

    1

    0

    1

    0

    1

    X

    X

    X

    1

    1

    1

    1

  • . * (Decoder) nx2n n 2n .

  • . * 2x4 2x4 A B D0, D1, D2 D3. D0=ABD1=ABD2=ABD3=AB

    A

    B

    D0

    D1

    D2

    D3

    0

    0

    1

    0

    0

    0

    0

    1

    0

    1

    0

    0

    1

    0

    0

    0

    1

    0

    1

    1

    0

    0

    0

    1

  • . * (Demultiplexer) 1x2n 2n , n . , /. / , .

  • . * 2x4 / 2x4 A B D0, D1, D2 D3. D0=A+BD1=A+BD2=A+BD3=A+B

    A

    B

    D0'

    D1'

    D2'

    D3'

    0

    0

    0

    1

    1

    1

    0

    1

    1

    0

    1

    1

    1

    0

    1

    1

    0

    1

    1

    1

    1

    1

    1

    0

  • . * n nx2n OR. :- - nx2n OR 1.

    n m nx2n m OR.

  • . * / n / nx2n NAND. n m / nx2n m NAND.

  • . *

  • . * (Multiplexer) 2nx1 2n n 1 .

    S

    I1

    I0

    Y

    0

    0

    0

    0

    0

    0

    1

    1

    0

    1

    0

    0

    0

    1

    1

    1

    1

    0

    0

    0

    1

    0

    1

    0

    1

    1

    0

    1

    1

    1

    1

    1

    S

    Y

    0

    I0

    1

    I1

    Y=I0S'+I1S

  • . * n 2nx1. n . O . .

  • . * F(A,B,C)=(1,3,5,6) 8x1 I0, I1, I2, I3, I4, I5, I6, I7, S2, S1, S0 Y. : S2=A, S1=B, S0=CO : I0=0, I1=1, I2=0, I3=1, I4=0, I5=1 I6=1, I7=0 : Y=F

  • . * . n 2nx1. n . O . .

  • . * n 2n-1x1. n-1 . n- 0 1, . .

    n m m 2n-1x1.

  • . * F(A,B,C)=(1,3,5,6) 4x1 I0, I1, I2, I3, S1, S0 Y.

  • . * B C : S1=B, S0=C, :

    O :I0=0, I1=1, I2=A, I3=A : Y=F

    I0

    I1

    I2

    I3

    A

    0

    1

    2

    3

    A

    4

    5

    6

    7

    0

    1

    A

    A

  • . * A B : S1=A, S0=B, :

    O :I0=C, I1=C, I2=C, I3=C : Y=F

    I0

    I1

    I2

    I3

    C

    0

    2

    4

    6

    C

    1

    3

    5

    7

    C

    C

    C

    C

  • . *FLIP-FLOP FLIP-FLOP FLIP-FLOP FLIP-FLOP FLIP-FLOPJK FLIP-FLOPT FLIP-FLOPD FLIP-FLOP

  • . * FLIP-FLOP v v o . v v v o o o ov o v o o v v ov oov o. o v ov v., flip-flop v o v oo oov v oov oo. oo o v o 1 o 0 v o o flip-flop v v.

  • . * FLIP-FLOP flip-flop o o o, v flip-flop o o Q o o o Q. flip-flop oo (clock), flip-flop, . (triggering). flip-flop CLEAR PRESET o v o v oo, v o o ooo.

  • . * FLIP-FLOP

    CLEAR

    PRESET

    0

    0

    0

    1

    1

    0

    1

    1

  • . * FLIP-FLOP flip-flop (clock) . . 0 1 . 1 0 .

  • . * flip-flop , . - 0 1 (Positive Going Transition - PGT) (positive edge) - 1 0 (Negative Going Transition - NGT) (negative edge)

  • . *JK FLIP-FLOP Q(t+1)=JQ'(t)+K'Q(t)

    J

    K

    Q(t+1)

    0

    0

    Q(t)

    0

    1

    0

    1

    0

    1

    1

    1

    Q(t)

    (Toggle)

    Q(t)

    Q(t+1)

    J

    K

    0

    0

    0

    X

    0

    1

    1

    X

    1

    0

    X

    1

    1

    1

    X

    0

  • . *T FLIP-FLOP Q(t+1)=TQ'(t)+T'Q(t)=TQ

    T flip-flop J-K flip-flop J K, J=T K=T

    T

    Q(t+1)

    0

    Q(t)

    1

    Q(t)

    (Toggle)

    Q(t)

    Q(t+1)

    T

    0

    0

    0

    0

    1

    1

    1

    0

    1

    1

    1

    0

  • . *D FLIP-FLOP Q(t+1)=D D flip-flop J-K flip-flop NOT, J=D K=D

    D

    Q(t+1)

    0

    0

    1

    1

    Q(t)

    Q(t+1)

    D

    0

    0

    0

    0

    1

    1

    1

    0

    0

    1

    1

    1

  • . *

  • . * (register) . flip-flop (1) bit . , n flip-flops n-bit . n bit n bit n flip-flops .

  • . * Y :- , flip-flops - (shift register), ()

  • . *

  • . * flip-flops . 0, AND 0 , flip-flops , . 1, flip-flops ( flip-flops), D0, D1, D2 D3 ( DO LSB D3 MSB) 4 flip-flops . Q1, Q2, Q3 Q4 flip-flops . (loading). . , flip-flops D3=1, D2=0, D1=1 D0=1, flip-flops Q3=1, Q2=0, Q1=1 Q0=1, 1011.

  • . * (shift register) , flip-flop . , flip-flop . , . flip-flop , . , .

  • . * :- - (serial-in, serial-out: SISO)- - (serial-in, parallel-out: SIPO)- - (parallel-in, serial-out: PISO)- - (parallel-in, parallel-out: PIPO)

  • . *

  • . * :- - (state) . .

  • . * :- - flip-flop . (master clock generator) (synchronization).

  • . * flip-flop ( n log2n flip-flop [2n-1+1,2n] n flip-flop) flip-flop (JK flip-flo, T flip-flo, D flip-flo) flip-flop

  • . *1. () :- (1) x- (4) a, b, c d : x=0 a b c d x=1 a b b c c d d a

  • . *2. , ( ) ( ), .

  • . *3. , , .

    x=0

    x=1

    a

    a

    b

    b

    b

    c

    c

    c

    d

    d

    d

    a

    AB

    a

    00

    b

    01

    c

    10

    d

    11

  • . *4. ., .

  • . *5. flip-flop (4) (n=4). n log2n flip-flop [2n-1+1,2n] n flip-flop., (2) flip-flop (log2n= log24=2).

  • . *6. flip-flop T flip-flop .

  • . *7.

    A(t)

    B(t)

    x(t)=0

    x(t)=1

    A(t+1)

    B(t+1)

    A(t+1)

    B(t+1)

    0

    0

    0

    0

    0

    1

    0

    1

    0

    1

    1

    0

    1

    0

    1

    0

    1

    1

    1

    1

    1

    1

    0

    0

  • . *

    A(t)

    B(t)

    x(t)

    A(t+1)

    B(t+1)

    0

    0

    0

    0

    0

    0

    0

    1

    0

    1

    0

    1

    0

    0

    1

    0

    1

    1

    1

    0

    1

    0

    0

    1

    0

    1

    0

    1

    1

    1

    1

    1

    0

    1

    1

    1

    1

    1

    0

    0

  • . * (2) T flip-flop T flip-flop A T flip-flop B . flip-flop : flip-flop flip-flop, :- T flip-flop A TA - T flip-flop B TB

  • . * T flip-flop, , .

    flip-flops

    A(t)

    B(t)

    x(t)

    A(t+1)

    B(t+1)

    TA

    TB

    0

    0

    0

    0

    0

    0

    0

    0

    0

    1

    0

    1

    0

    1

    0

    1

    0

    0

    1

    0

    0

    0

    1

    1

    1

    0

    1

    1

    1

    0

    0

    1

    0

    0

    0

    1

    0

    1

    1

    1

    0

    1

    1

    1

    0

    1

    1

    0

    0

    1

    1

    1

    0

    0

    1

    1

  • . *8. flip-flop TA TB flip-flops A(t) B(t) flip-flop x(t) . flip-flops :TA=B(t)x(t) T flip-flop ATB=x(t) T flip-flop B A(t) B(t) flip-flop x(t) .

  • . *9. flip-flop. :- (1) x- (2) T flip-flop A B-

  • . * flip-flop ( AND ). x B T flip-flop B ( B T flip-flop B). flip-flop. flip-flop (synchronization) .

  • . *

  • . * NAND NOR

  • . * NAND NAND : Y=S+Ry SR=0

  • . * NOR NOR : Y=S+Ry SR=0

  • . * . ,

  • . * () (1) NAND, :- (2) x1 x2- (2) : y : Y :Y= yx1+x1x2

  • . *1. :Y= x1y+x1x2

  • . *2. :Y=S+Ry=x1x2+ x1y S=x1+x2 R=x1

  • . *3.

    , :SR=x1x20 , . ( ) Karnaugh .

  • . * Karnaugh

    Karnaugh , ( ): Y= x1y+x1x2=x1y+x1x2+yx2

    x1

    00

    01

    11

    10

    0

    1

    y

    1

    1

    1

    1

    x2

  • . * ( ), :Y=S+Ry= x1y+x1x2+yx2 S=x1+x2 R=x1+x2 , :SR=0 , .

  • . *4.

    () :- (2) x1 x2- (1) NAND- S=x1+x2 R=x1+x2 .

  • . *

  • . * KAI

  • . * (Counters) : (asynchronous counters) (synchronous counters)

    :

  • . * flip-flop, , , flip-flop, flip-flop , (ripple) flip-flop .

    , flip-flop, ( ), flip-flop .

  • . * ( ). modulo ( 0 -1). 4 bit 16 ( 0 15) modulo 16. BCD 10 ( 0 9) modulo 10 .

  • . * . , , flip-flop (synchronization) . .

  • . *1. 0-1-2-3-4-5-6-7 .

  • . *2.

  • . *3.

    0

    1

    1

    2

    2

    3

    3

    4

    4

    5

    5

    6

    6

    7

    7

    0

    ABC

    0

    000

    1

    001

    2

    010

    3

    011

    4

    100

    5

    101

    6

    110

    7

    111

  • . *4. ., .

  • . *5. flip-flop (8) (n=8). n log2n flip-flop [2n-1+1,2n] n flip-flop., (3) flip-flop (log2n= log28=3).

  • . *6. flip-flop T flip-flop .

  • . *7.

    A

    B

    C

    A

    B

    C

    0

    0

    0

    0

    0

    1

    0

    0

    1

    0

    1

    1

    0

    1

    0

    0

    1

    1

    0

    1

    1

    1

    0

    1

    1

    0

    0

    1

    0

    1

    1

    0

    1

    1

    1

    1

    1

    1

    0

    1

    1

    1

    1

    1

    1

    0

    0

    1

  • . *

    flip-flop

    A

    B

    C

    A

    B

    C

    TA

    TB

    TC

    0

    0

    0

    0

    0

    1

    0

    0

    1

    0

    0

    1

    0

    1

    1

    0

    1

    1

    0

    1

    0

    0

    1

    1

    0

    0

    1

    0

    1

    1

    1

    0

    1

    1

    1

    1

    1

    0

    0

    1

    0

    1

    0

    0

    1

    1

    0

    1

    1

    1

    1

    0

    1

    1

    1

    1

    0

    1

    1

    1

    0

    0

    1

    1

    1

    1

    0

    0

    1

    1

    1

    1

  • . *8. flip-flop TA, TB TC flip-flop A, B C flip-flop.

    TA, TB TC flip-flop :TA=BC, T flip-flop ATB=C, T flip-flop BTC=1, T flip-flop C

  • . *9. :- (3) T flip-flops A, B C- flip-flop ( AND ). flip-flop (synchronization) . .

  • . *CPTAAND Q

    T Q

    T Q

    TABC1TBTC

  • . * [1] MANO M. M., , , 2005[2] Brown S, Vranesic Z., VHDL, , 2001 [3] ., , , 2007[4] ., , Gutenberg, 2008

  • . * [1] Boole G., An Investigation of the Laws of Trougth, New York: Dover, 1954.[2]Cavanagh J. J., Digital Computer Arithmetic, New York: McGraw-Hill, 1984.[3]Huntington E. V., Sets of Independent Postulates for the Algebra of Logic, Trans. Am. Math. Soc., Vol. 5, pp.288-309, 1904.[4]Karnaugh M., A Map Method for Synthesis of Combinational Logic Circuits, Trans. AIEE, Comm. and Electron., Vol. 72, Part I, pp. 593-599, 1953.[5] Mano M. M., Computer Engineering: Hardware Design, Englewood Cliffs, NJ: Prentice-Hall, 1988.[6]Mano M. M., Computer System Architecture, 2nd Ed., Englewood Cliffs, NJ: Prentice-Hall, 1982.[7]Mano M. M., Digital Design, 2nd Ed., Englewood Cliffs, NJ: Prentice-Hall, 1992.[8] McCluskey E. J., Logic Design Principles, Englewood Cliffs, NJ: Prentice-Hall, 1986.[9] Peatman J. B., Digital Harware Design, New York: McGraw-Hill, 1980.[10] Roth C. H., Fundamentals of Logic Design, 3rd Ed., New York: West Publishing Co., 1985.

  • . *DATABOOKSCMOS Logic Databook, National, 1988.Data Acquisition Databook, National, 1993.Linear Application Specific IC's Databook, National, 1993.LS/S/TTL Logic Databook, National, 1989.

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