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III. VLSI

Matthias Bucher

2014

Bucher electronics.tuc.gr

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Figure A.1 Silicon ingot and wafer slices.

Silicon wafers

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Figure A.2 (a) An 8-pin plastic dual-in-line IC package, (b) A 16-pin surface mount package.

Packaging

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Figure A.3 A typical n-well CMOS process flow.

(a) Define n-well diffusion (mask #1)

(b) Define active regions (mask #2)

Fabrication process (i)

(c) LOCOS oxidation

(d) Polysilicon gate (mask #3)

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Figure A.3 A typical n-well CMOS process flow.

(g) Contact holes (mask #6) (e) n+ diffusion (mask #4)

(f) p+ diffusion (mask #5)

Fabrication process (ii)

(h) Metallization (mask #7)

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Figure A.4 Cross-sectional diagram of an n- and p-MOSFET.

NMOS and PMOS cross-section

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Figure A.7 A pn junction diode in an n-well CMOS process.

pn Junction

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Figure A.9 A lateral pnp transistor.

Lateral npn Transistor

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Figure A.11 Cross-sectional diagram of a symmetrical self-aligned npn SiGe heterojunction bipolar transistor (HBT).

SiGe Heterojunction Bipolar Transistor (HBT)

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Figure A.5 Cross sections of resistors of various types available from a typical n-well CMOS process.

Resistors (i)

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Figure A.10 p-Base and pinched p-base resistors.

Resistors (ii)

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Figure A.6 Interpoly and MOS capacitors in an n-well CMOS process.

MIM and MOSVAR capacitors

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Figure A.8 Cross-sectional diagram of a BiCMOS process.

BiCMOS cross section

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Figure A.13 Cross section along the plane AA of a CMOS inverter.

CMOS inverter cross-section

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Figure A.12 A CMOS inverter schematic and its layout.

CMOS inverter layout

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Figure A.14 A set of photomasks for the n-well CMOS inverter. Note that each layer requires a separate plate: (a), (d),

(e), and (f) dark-field masks; (b), (c), and (g) clear-field masks.