© 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission...

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical : Work function (Φ) mismatch Thermal : Debye (v,Θ) mismatch ++ ?? ++ ?? f BE (ω) ω g(E) g(ω) ω g(ω) ω D,2 ω D,1 interface reflected 1 l , t 1 ,or t 2 incident l t 1 t 2 transm itted l t 1 t 2 2 critical angle interface reflected 1 l , t 1 ,or t 2 incident l t 1 t 2 transm itted l t 1 t 2 2 critical angle µ 1 µ 2 µ 1 2 = ?

Transcript of © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission...

Page 1: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 1

Summary of Boundary Resistance

thermionic emission

tunneling or reflectionfFD(E)

E

Electrical: Work function (Φ) mismatch Thermal: Debye (v,Θ) mismatch

++ ?? ++ ??

fBE(ω)

ω

g(E)

g(ω)

ω

g(ω)

ωD,2

ωD,1

interface

reflected

1

l , t1 , or t2

incidentl

t1

t2

transmitted

l

t1t2

2

critical angle

interface

reflected

1

l , t1 , or t2

incidentl

t1

t2

transmitted

l

t1t2

2

critical angle

µ1

µ2

µ1-µ2 = ?

Page 2: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 2

Acoustic vs. Diffuse Mismatch Model

interface

reflected

1

l , t1 , or t2

incidentl

t1

t2

transmitted

l

t1t2

2

critical angle

interface

reflected

1

l , t1 , or t2

incidentl

t1

t2

transmitted

l

t1t2

2

critical angle

Acoustic ImpedanceMismatch (AIM)

= (ρv)1/(ρv)2

Acoustic Mismatch Model (AMM) Khalatnikov (1952)

Diffuse Mismatch Model (DMM) Swartz and Pohl (1989)

DiffuseSpecular

Diffuse Mismatch= (Cv)1/(Cv)2

Snell’s lawwith Z = ρv

1 22

1 2

4

( )

Z ZT

Z Z

(normal incidence)

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 3

Debye Temperature Mismatch

DMM

Stevens, J. Heat Transf. 127, 315 (2005)Stoner & Maris, Phys. Rev. B 48, 16373(1993)

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General Approach to Boundary Resistance

Flux J = #incident particles x velocity x transmission prob.

transmission

fFD(Ex)

Ex

0

exp 2 ( )L

WKBT k x dx

A BE||

#incident ( )A B B A A B A BJ J J g g f f T E dE

0 L

More generally:fancier version of

Landauer formula!

ex: electron tunneling

1, ,

eB e B e

dJG R

dV 1

, ,th

B th B th

dJG R

dT

(conductance)

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 5

Band-to-Band Tunneling Conduction

• Assuming parabolic energy dispersion E(k) = ħ2k2/2m*

• E.g. band-to-band (Zener) tunneling

in silicon diode

* 3/24 2( ) exp

3x x

x

m ET E

q F

F = electric field

3 * 3/2*

3 2

4 22exp

4 3eff x G

BBG

q FV m EmJ

E q F

See, e.g. Kane, J. Appl. Phys. 32, 83 (1961)

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Thermionic and Field Emission (3D)

µ1

µ2µ1-µ2 = qV

thermionic emission

tunneling (field emission)Φ

* 3/23 2 4 2exp

8 3x

FN

mq FJ

h q F

field emission a.k.a. Fowler-Nordheim tunneling

see, e.g. Lenzlinger, J. Appl. Phys. 40, 278 (1969)S. Sze, Physics of Semiconductor Devices, 3rd ed. (2007)

* 22

3

4expx B

TEB

m k q qJ T

h k T

F

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 7

The Photon Radiation Limit

Swartz & Pohl, Rev. Mod. Phys. 61, 605 (1989)

Acoustic analog ofStefan-Boltzmann constant

Phonons behave like photons at low-Tin the absence of scattering (why?)

Heat flux:

ci = sound velocities (2 TA, 1 LA)

what’s the temperature profile?

Page 8: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 8

Phonon Conductance of Nanoconstrictions

Prasher, Appl. Phys. Lett. 91, 143119 (2007)

1) a >> λ τ = cos(θ)

λ = dominant phonon wavelength

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 9

Phonon Conductance of Nanoconstrictions

Prasher, Appl. Phys. Lett. 91, 143119 (2007)

2) a << λ

λ = dominant phonon wavelength

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Why Do Thermal Boundaries Matter?

• Because surface area to volume ratio is greater for nanowires, nanoparticles, nanoconstrictions

• Because we can engineer metamaterials with much lower “effective” thermal conductivity than Mother Nature

lmin=50100

50

n=2, l=50n=1, l=100

n=2, l=100n=3, l=66

n=1, l=200

n=4, l=50

nl 2d cos

(i)

(ii)

(i)

wavevector, K

freq

uen

cy, w

(ii)

wavevector, K

freq

uen

cy, w

(A) (B)

lmin=50100

50

n=2, l=50n=1, l=100n=2, l=50n=1, l=100

n=2, l=100n=3, l=66

n=1, l=200

n=4, l=50

n=2, l=100n=3, l=66

n=1, l=200

n=4, l=50

nl 2d

(i)

(ii)

(i)

wavevector, K

freq

uen

cy, w

(i)(i)

wavevector, K

freq

uen

cy, w

wavevector, K

freq

uen

cy, w

(ii)

wavevector, K

freq

uen

cy, w

(ii)(ii)

wavevector, K

freq

uen

cy, w

wavevector, K

freq

uen

cy, w

(A) (B)TEM of superlattice

source: A. Majumdar

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 11

Because of Thermoelectric Applications

• No moving parts: quiet and reliable• No Freon: clean

Courtesy: L. Shi, M. Dresselhaus

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Thermoelectric Figure of Merit (ZT)

11

/1COPmax

m

chm

ch

c

zT

TTzT

TT

T

Coefficient of Performance

where ZT is…

TS

ZT2

Seebeck coefficient

Electrical conductivity

Thermal conductivity

Temperature

0

1

2

0 1 2 3 4 5

ZTC

OP

ma

x

Bi2Te3

Freon (CFCs)

TH = 300 KTC = 250 K

Courtesy: L. Shi

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 13

ZT State of the Art

• Goal: decrease k (keeping σ same) with superlattices, nanowires or other nanostructures

• Nanoscale thermal engineering!

5

Harman et al., Science 297, 2229

Venkatasubramanian et al. Nature 413, 597

Bi2Te3/Sb2Te3 Superlattices

2.5-25nm

Quantum dot superlattices

Courtesy: A. Majumdar, L. Shi

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 14

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 15

Nanoscale Thermometry

Reviews: Blackburn, Semi-Therm 2004 (IEEE)Cahill, Goodson & Majumdar, J. Heat Transfer (2002)

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 16

Typical Measurement Approach

• For nanoscale electrical we can still measure I/ΔV = AJq/ΔV

• For nanoscale thermal we need Jth/ΔT, but there is NO good, reliable nanoscale thermometer

• Typically we either:a) Measure optical reflectivity change with ΔT

b) Measure electrical resistivity change with ΔT

(after making sure they are both calibrated)

• Must know the thermal flux Jth

g

Pt

SiO2

Page 17: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 17

The 3ω Method (thin film cross-plane)

D. Cahill, Rev. Sci. Instrum. 61, 802 (1990)T. Yamane, J. Appl. Phys. 91, 9772 (2002)

I0 sin(wt)

L 2b

Substrate

Metal line

f

s

s LbkPdi

b

D

kLP

T24

2ln21

ln21

)2(2

w

w

• I ~ 1w• T ~ I2 ~ 2w• R ~ T ~ 2w• V3ω ~ IR ~ 3wVThin film

where α is metal line TCR

Page 18: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 18

3ω Method Applications…

Thin crystalline Si films

Ju and Goodson, Appl. Phys. Lett. 74, 3005 (1999)

Compare temperature rise of metal line for different linewidths, deduce anisotropicpolymer thermal conductivity

Ju, Kurabayashi, Goodson, Thin Solid Films 339, 160 (1999)

SuperlatticesSong, Appl. Phys. Lett. 77, 3154 (2000)

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The 3ω Method (longitudinal)

Substrate

WireI0 sin(wt)

V

Lu, Yi, Zhang, Rev. Sci. Instrum. 72, 2996 (2001)

• 3w mechanism: ΔT~ V2/k and R ~ Ro + αΔT

• Low frequency: V(3ω) ~ 1/k

• High frequency: V(3ω) ~ 1/C

• Tested for a 20 μm diameter Pt wire

• Results for a bundle of MW nanotubes:

C ~ linear T dependence, low k ~ 100 W/mK

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 20

Another Suspended Bridge Approach

SiNx beam

Pt heater line

Suspended island

Multiwall nanotube

Pt heater line

Source: L. Shi

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 21

Measurement Scheme

10 nm multiwall tube

Island

Beam

Pt heater line

Th Ts

t Ts

Rs

Rh QH = IRH

Tube

I

Gt = kA/L

0

02h l s

th s h s

Q Q T TG

T T T T T

Thermal Conductance:

VTE

Thermopower:Q = VTE/(Th-Ts)

QL = IRL

Environment T0

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 22

Multiwall Nanotube Measurement

14 nm multiwall tube

6

4

2

0

Res

ista

nce

(k

)

3002001000

Temperature (K)

Resistance of the Pt line

0.4

0.2

0

R

/R(%

)

2.01.51.00.50.0

Power(

m

W )

0.6

Rh

Rs

T

(K)

2

1

0

m

Resistance vs. Joule Heat

Temperature (K)

k (1

03W

/m K

)

3

2

1

0

300200100

3

2

1

0

300200100

l ~ 0.5 mm

T2

Measurement result

Cryostat: T : 4-350 K P ~ 10-6 torr

L. Shi, J. Heat Transfer, 125, 881 (2003)

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 23

Scanning Thermal Microscopy (SThM)

• Sharp temperature-sensing tip mounted on cantilever

• Scan in lateral direction, monitor cantilever deflection

• Thermal transport at tip is key (air, liquid, and solid conduction)

TA

TT

TS

Source: L. Shi, Appl. Phys. Lett. 77, 4296 (2000)

Page 24: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 24

SThM Applied to Multi-Wall Nanotube

• Must understand sample-tip heat transfer

• Note arbitrary temperature units here (calibration was not possible)

• Note Rtip ~ 50 nm vs. d ~ 10 nm

Source: L. Shi, D. Cahill

Page 25: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 25

Scanning Joule Expansion Microscopy

• AFM cantilever follows the thermo-mechanical expansion of periodically heated (ω) substrate

• Ex: SJEM thermometry images of metal interconnects

• Resolution ~10 nm and ~degree CSource: W. P. King

V

B

A

X-Y-ZPiezoelectric

ScannerFeedback

TopographyImage

ThermalExpansion

Image

Lock-inAmplifier

Ref.

Mirror

Fixed LaserSource

Photodiode

Interconnect

ThermalImage Thermal expansion image at 20 kHz

Thermal expansion image at 100 kHz

5 mm5 mm

5 mm5 mm

Thermal expansion image at 20 kHz

Thermal expansion image at 100 kHz

5 mm5 mm

5 mm5 mm

Page 26: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 26

Thermal Effects on Devices

• At high temperature (T↑)– Threshold voltage Vt ↓ (current ↑)

– Mobility decrease µ ↓ (current ↓)

– Device reliability concerns

• Device heats up during characterization (DC I-V)– Temperature varies during digital and analog operation

– Hence, measured DC I-V is not “true” I-V during operation

– True whenever tthermal >> telectrical and high enough power

– True for SOI-FET (perhaps soon bulk-FET, CNT-FET, NW-FET)

• How to measure device thermal parameters at the same

time as electrical ones?

)( 00 TTVV tt mm )/( 00 TT

Page 27: © 2010 Eric Pop, UIUCECE 598EP: Hot Chips Summary of Boundary Resistance 1 thermionic emission tunneling or reflection f FD (E) E Electrical: Work function.

© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 27

Measuring Device Thermal Resistance

• Noise thermometry– Bunyan 1992

• Gate electrode resistance thermometry– Mautry 1990; Goodson/Su 1994

• Pulsed I-V measurements– Jenkins 1995, 2002

• AC conductance measurement– Lee 1995; Tenbroek 1996; Reyboz 2004; Jin 2001

Note: these are electrical, non-destructive methods

∆T = P × RTH

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 28

Noise Thermometry

• Body-contacted SOI devices– L = 0.87 and 7.87 µm

– tox = 19.5 nm, tSi = 0.2 um, tBOX = 0.42 um

• Bias back-gate accumulation (R) at back interface

• Mean square thermal noise voltage ‹vn›2 = 4kBTRB

• Frequency range B = 1-1000 Hz

• Measure R and ‹vn› at each gate & drain bias

• T = T0 + RTHIDVD (RTH ~ 16 K/mW)

Bunyan, EDL 13, 279 (1992)

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 29

Gate Electrode Resistance Thermometry

• Gate has 4-probe configuration

• Make usual I-V measurement…

• Gate R calibrated vs. chuck T

• Measure gate R with device power P

• Correlate P vs. T and hence RTH

Mautry 1990; Su-Goodson 1994-95

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 30

Pulsed I-V Measurement

• Normal device layout

• 7 ns electric pulses, 10 µs period

• Device can cool during long thermal time constant (50-100 ns)

• High-bandwidth (10 GHz) probes

• Obtain both thermal resistance and capacitance

Jenkins 1995, 2002

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 31

AC Conductance Measurement

• No special test structure

• Measure drain conductance

• Frequency range must span all

device thermal time constants

• Obtain both RTH and CTH

• Thermal time constant (RTHCTH) is

bias-independent

Lee 1995; Tenbroek 1996; Reyboz 2004; Jin 2001

gDS = ∂ID / ∂VDS

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 32

0.1

1

10

100

1000

10000

100000

0.01 0.1 1 10L (mm)

RT

H (

K/m

W)

Device Thermometry Results Summary

Cu

GST

SiO2

Si

Silicon-on-Insulator FET

Bulk FET

Cu Via

Phase-change Memory (PCM)

Single-wall nanotube SWNT

Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006).

High thermal resistances:

• SWNT due to small thermal conductance (very small d ~ 2 nm)

• Others due to low thermal conductivity, decreasing dimensions, increased role of interfaces

Power input also matters:

• SWNT ~ 0.01-0.1 mW

• Others ~ 0.1-1 mW

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© 2010 Eric Pop, UIUC ECE 598EP: Hot Chips 33